Abstract: The invention relates to a charge detector semiconductor component in the form of a structure provided on a semiconductor material, which component comprises a non-volatile storage cell in the form of a MOS field effect transistor with a transistor gate and a MOS capacitor with a capacitor gate. The invention further relates to a system comprising a charge detector semiconductor component and a reference semiconductor component. The invention further relates to a wafer as well as to the use of a wafer with a plurality of charge detector semiconductor elements and/or systems. Finally, the invention relates to a method for the qualitative and quantitative measurement of the charging of a wafer during processing of the wafer. According to the invention, it is possible to measure exactly the charge that has arisen during the processing of wafers and the manufacture of semiconductor components, in particular owing to plasma and ion implantation processes.

Abstract: The invention relates to a charge detector semiconductor component in the form of a structure provided on a semiconductor material, which component comprises a non-volatile storage cell in the form of a MOS field effect transistor with a transistor gate and a MOS capacitor with a capacitor gate. The invention further relates to a system comprising a charge detector semiconductor component and a reference semiconductor component. The invention further relates to a wafer as well as to the use of a wafer with a plurality of charge detector semiconductor elements and/or systems. Finally, the invention relates to a method for the qualitative and quantitative measurement of the charging of a wafer during processing of the wafer. According to the invention, it is possible to measure exactly the charge that has arisen during the processing of wafers and the manufacture of semiconductor components, in particular owing to plasma and ion implantation processes.

Abstract: An arrangement for improving the ESD protection in a CMOS buffer includes a plurality of PMOS transistors (31 to 37) and a plurality of NMOS transistors (41-47) which are connected in series with the PMOS transistors and have a finger width WN which is larger than the finger width WP of the PMOS transistors in order to be capable of withstanding an increased current load in the case of an electrostatic discharge.

Abstract: An integrated circuit comprising a substrate with analog and digital sub-circuits provided with different supply terminals, including Vdd and Vss supply terminals for the analog part and a Vdd supply terminal for the digital part, as well as a common substrate terminal or ground terminal. In the substrate, an element with diode function is formed between the Vdd and Vss supply terminals of an analog sub-circuit, which element with diode function comprises a cathode part connected to the Vdd supply terminal and an anode part connected to the Vss supply terminal of the relevant analog sub-circuit. The supply terminals are further connected to the substrate terminal or ground terminal via over-voltage protection circuits, said over-voltage protection circuits for the relevant analog sub-circuit being embodied so as to be active only for positive over-voltages on a supply terminal with respect to the substrate.

Abstract: The invention relates to an arrangement for improving the ESD protection in a CMOS buffer which includes a plurality of PMOS transistors (31 to 37) and a plurality of NMOS transistors (41-47) which are connected in series with the PMOS transistors and have a finger width WN which is larger than the finger width WP of the PMOS transistors in order to be capable of withstanding an increased current load in the case of an electrostatic discharge.