Abstract: A wireless local area network apparatus includes a transmitter and a receiver in which operation of the receiver is accurately synchronized with periodic signals from the transmitter. The periodic signals contain timing data indicating the state of a timer in the transmitter at the time the signal containing that data was transmitted and this timing data is retrieved from the signal when received by the receiver and loaded in a timer for controlling operation of the receiver.

Abstract: A wireless local area network apparatus includes a transmitter and a receiver in which operation of the receiver is accurately synchronized with periodic signals from the transmitter. The periodic signals contain timing data indicating the state of a timer in the transmitter at the time the signal containing that data was transmitted and this timing data is retrieved from the signal when received by the receiver and loaded in a timer for controlling operation of the receiver.

Abstract: The timing of a carrier signal is tracked in a receiver. The receiver receives a signal produced by a transmitter having a single frequency source which is used to generate a reference clock frequency and a carrier signal frequency, there being a fixed, predetermined relationship between the reference and carrier frequencies. In the receiver there is a single frequency source which is used to generate a reference clock frequency and a carrier reference signal frequency, there being a fixed, predetermined relationship between the reference and carrier reference frequencies. The fixed, predetermined relationship in the transmitter and the receiver is the same.

Abstract: A system for, and method of, generating a spread spectrum code position modulated waveform and a wireless local area network (LAN) containing the system or the method. The system includes: (1) a spread-spectrum encoder that receives and encodes portions of an information signal with a multi-chip code having a predetermined length to create therefrom a stream of sequences, each of the sequences having the predetermined length and (2) a transmitter that periodically transmits the each of the sequences at a time interval that differs from the predetermined length, a data rate of transmission of the information signal thereby allowed to increase.

Abstract: A receiver, and a method for operating the receiver, for a station in a wireless local area network using a common wireless communication channel and employing a CSMA/CA (carrier sense multiple access with collision avoidance) protocol includes various modes. In normal mode, the receiver follows typical states in order to detect a message and demodulate data from the message properly. Meanwhile, a process implements a message-in-message (MIM) mode when an energy increase above a specified level is detected. While in the MIM mode, if a carrier is detected, the energy increase is caused by a new message; otherwise, the energy increase is caused by an interfering station. If the carrier is detected, the receiver begins retraining so that it can start receiving the new message as soon as the first message ends. If no carrier is detected, the receiver waits a specified time to detect a carrier or for the end of the first message, after which the receiver returns to the beginning of the normal mode.

Abstract: For use in an automatic gain control that receives a digital signal from a digital circuit having a given dynamic range and develops therefrom a gain signal to be applied to a variable gain amplifier, an analyzing circuit for, and method of, determining a magnitude of the gain signal.

Abstract: For use in a direct sequence spread spectrum ("DSSS") receiver adapted to receive a differential phase shift keyed ("DPSK") packet on a channel, the DPSK packet having a training preamble and a data portion, a system to improve detection of the packet under degraded channel conditions, comprising: (1) a detection circuit that derives phase information from symbols in the packet and a weight that is a function of an estimated power profile for the channel and (2) a computation circuit that computes a weighted average for the phase information using the weight, the weighted average being power profile-based to allow the receiver to detect the data contained in the packet more reliably under the degraded channel conditions.

Abstract: A wireless pointing device which sits in the palm of a user's hand. The palm mouse includes a first portion which includes a ball for generating pointing signals, a control circuit for processing the pointing signals, a top section having a top surface which is generally ovoid in shape, and a bottom section having a bottom surface which is generally flat in shape and which contains an aperture through which the ball protrudes. A second portion includes a J-shaped flexible member attached to the first portion for cupping the hand. A communication circuit includes a transmitter within the first portion, a first antenna within the J-shaped member, a power supply within the first portion, a receiver coupled to the computer, and a second antenna coupled to the receiver. A preferred embodiment of the palm mouse has at least one switch on the J-shaped member, which is activated by the user's thumb.

Abstract: A wireless LAN includes first stations adapted to operate at a 1 or a 2 Mbps data rate and second stations adapted to operate at a 1,2,5 or 8 Mbps data rate. The 1 and 2 Mbps rates use DBPSK and DQPSK modulation, respectively. The 5 and 8 Mbps rates use PPM/DQPSK modulation. All four data rates use direct sequence spread spectrum (DSSS) coding. All transmitted messages start with a preamble and header at the 1 Mbps rate. The header includes fields identifying the data rate for the data portion of the message, and a length field. For a 2 Mbps transmission the length field identifies the number of bytes in the data field. For a 5 or 8 Mbps the length field identifies the number of bytes in the data field which, if transmitted at 2 Mbps, would take the same transmission time of the data field, and is thus a fraction 2/5 or 2/8 of the actual number of the bytes. With this arrangements, all the stations are interoperable in a co-existent manner in the LAN.

Abstract: In a local area network station (12) for a wireless LAN, a threshold level circuit (62) includes a register (134) which stores a threshold value. The station receiver (42) monitors the transmission channel and provides a receive level signal indicative of the signal level received. Transmission of a data frame by the station transmitter (46) is permitted or deferred according as the receive level signal value is below or above the threshold level, regardless of whether or not the received signal derives from a transmission by a station in the receiving station's own LAN. The threshold is dynamically updated whenever the station (12) receives a data frame from its own LAN. An improved utilization of the wireless transmission channel is achieved.

Abstract: A local area network station (12) includes a transceiver (20) adapted to transmit and receive signals using electromagnetic radiation on a wireless communication link. The station (12) utilizes a CSMA/CD communications controller (22) in a CSMA/CA (collison avoidance) technique wherein deferred data frames are transmitted after a random number of backoff slots periods. A plurality of antennas (14, 16) is employed, with the antenna having the best receive conditions being selected for reception of a data frame. The antennas having a slotting control (200) which is synchronized with the backoff slotting to provide a short carrier detect time and hence high throughpout.

Abstract: A radio LAN station is provided for receiving information frames including start and end delimiters and user data therebetween. The start and end delimiters include both data symbols and special non-data symbols. The data symbols and non-data symbols being transmitted to the radio LAN station are sent thereto via a spread spectrum signal. The data symbols and the non-data symbols are spread via first and second spreading codes, respectively. The receiving radio LAN station includes first and second correlators which respectively correlate the received spread spectrum signal against the first spreading code to retrieve the data symbols and against the second spreading code to retrieve the non-data symbols. Rectangular representations of the received data and non-data symbols are thus produced and are converted to polar form via appropriate rectangular to polar converters. The polar representations of the data and non-data symbols respectively exhibit a vector length Z and a vector length Z'.

Abstract: A local area network (10) utilizes a wireless transmission link and has network stations (12) each having two differently polarized antennas (14, 16). Data transmission utilizes a spread spectrum code and in the receiver, correlator outputs are utilized in an integrator and registers circuit (54) to provide correlator output sample values integrated over a plurality of symbol intervals. These values are stored in registers (156) the contents of which are utilized to determine a peak value and a total value which are applied to a spike quality determination circuit (78) including a look-up table (200). The resultant spike quality output value represents the quality of the received signal and is utilized for carrier detection and for antenna selection.

Abstract: A local area network station for receiving data symbols encoded in a spread spectrum code and transmitted over a wireless channel includes in-phase and quadrature correlators (42, 44) the output signals of which are used to address a look-up table (50) for conversion to amplitude and phase sample signals. Corresponding amplitude sample signals are integrated and stored in a plurality of registers (96) and for each symbol, the register (96) storing the maximum value is ascertained to identify the associated sample number, which is stored in a sample number register (160). This sample number is utilized to determine the time of a symbol clock signal (RXCLK) used for clocking the received data.

Abstract: In a delay measuring circuit (10), an input clock signal (13) is applied to a multitapped delay line (14), the output taps of which are connected to a switch (26) which selects one of the switch inputs for connection to a phase comparator (34) which compares the input clock signal (13), delayed in a delay device (38) to compensate for the delay inherent in the switch (26), with the output of the switch (26). The input clock signal is also applied to a counter (22), and when the phase comparator (34) detects a phase match, the counter value is stored in a latch (32), the counter (22) is reset to a predetermined value, and the counting procedure resumed. The latch (32) thus always stores a value dependent on the delay of an individual delay cell (16-l to 16-N). This stored value can be applied to various uses, such as in a timing watchdog circuit or for generating accurate delays.

Abstract: A digital phase lock loop decoder for use in decoding Manchester encoded data operates at an internal clock speed having a speed equal to the data rate of the encoded data. The decoder includes a first sampling circuit for providing signals based on the clock speed of the encoded data, a delay circuit for generating delayed clock signals relative to the clock speed of the encoded data, a second sampling circuit for sampling the encoded data based on the delayed clock signals, a feedback circuit for generating clock signals whose phase corresponds with the phase of the delayed clock signals and a storage for outputting decoded data signals corresponding to the encoded data utilizing the delayed clock signals.

Abstract: In a digital data receiver (80) for demodulating a direct sequence spread spectrum differential phase shift keyed data signal, the signal is applied to the input transducer (140) of a SAW device (100) which has first and second output transducers (142, 144) spaced apart on the SAW substrate (130) so as to produce first and second output signals on output lines (102, 104), which are relatively delayed by a time corresponding to a symbol period. The output transducers are of identical construction and are matched to the spread spectrum code utilized in the data signal. Thus, a single SAW device (100) effects both correlation and delay. The output signals on the output lines (102, 104) are processed by a circuit including multipliers (106, 110) and a phase shifter (108) to produce output data signals representing the received data.

Abstract: An automatic gain control circuit suitable for use in a modem receiver for receiving a modulated carrier representing data, includes a variable gain amplifier adapted to receive an input signal and coupled to an output amplifier providing the gain controlled output and also coupled to a level detector which provides a high level output signal whenever the input thereto exceeds a reference level, such output signal causing an attack operation wherein a control current generator provides an exponentially decreasing control current for an operational transconductance amplifier included in the variable gain amplifier. When the level detector output is high for more than a predetermined time a noise hit protection circuit is effective to inhibit the attack operation for a further predetermined period of time, thereby alleviating the adverse effect of a noise pulse.

Abstract: A method and apparatus for synchronizing a digital data demodulator to a received phase modulation carrier signal in which the carrier signal is phase shifted during each modulation period of the carrier to represent one of four pairs of binary bits or dibits. A first dibit clock is adjusted to the phase of a reference dibit clock whose output is used to synchronize the demodulator in establishing the location of the modulation period of the incoming carrier. In order to overcome errors found in the decoding of the carrier signal, the adjustment of the dibit clock is suppressed when the dibits 00 and 10 are being decoded. With this construction, it was found that the dibit clock may run out of synchronization if long strings of zero characters (dibits 00) are received. In order to solve this problem, a second dibit clock is employed which is adjusted on dibits 00.