Abstract: An apparatus may include an internal charge pump within an integrated circuit package, an external pin positioned at an exterior of the integrated circuit package, and a select circuit configured to operate independently from the internal charge pump and located within the integrated circuit package, wherein the select circuit is configurable to selectively couple at least one of the internal charge pump and the external pin to a transmit (TX) sensor electrode.

Abstract: An apparatus may include an internal charge pump within an integrated circuit package, an external pin positioned at an exterior of the integrated circuit package, and a select circuit configured to operate independently from the internal charge pump and located within the integrated circuit package, wherein the select circuit is configurable to selectively couple at least one of the internal charge pump and the external pin to a transmit (TX) sensor electrode.

Abstract: An active integrator for sensing capacitance of a touch sense array is disclosed. The active integrator is configured to receive from the touch sense array a response signal having a positive portion and a negative portion. The response signal is representative of a presence or an absence of a conductive object on the touch sense array. The active integrator is configured to continuously integrate the response signal.

Abstract: An apparatus includes a reconfigurable charge pump including charge pump cells configurable into multiple different arrangements. The apparatus includes a control device configured to select a first arrangement of the charge pump cells from the multiple different arrangements based, at least in part, on an input voltage received by the reconfigurable charge pump and requested parameters of a drive signal for a touch screen panel. The reconfigurable charge pump can boost the input voltage based, at least in part, on the first arrangement of the charge pump cells. The control device can generate the drive signal according to the requested parameters based on the boosted input voltage.

Abstract: A compensation circuit may include a current source configured to control an amplitude of a current pulse, a memory configured to store a plurality of duration values each corresponding to a set of one or more sensor electrodes of a plurality of sensor electrodes, and a pulse width controller configured to control a duration of the current pulse based on a first duration value of the plurality of duration values, and to apply the current pulse to a compensation node of a capacitance sensor during a measurement cycle for a first set of one or more sensor electrodes, where the first set of one or more sensor electrodes corresponds to the first duration value.

Abstract: A circuit for generating a voltage is disclosed. The voltage has an amplitude greater than an available power supply. The circuit includes a driver to supply the voltage on an output terminal to an electrode of a touch sense array. The circuit also includes a charge pump array coupled to the driver. The charge pump array includes an array of charge pumps to supply an input voltage to the driver. The circuit also includes a feedback circuit coupled to the charge pump array. The feedback circuit is configured to measure the input voltage and to select different combinations of the array of charge pumps to maintain the voltage on the output terminal.

Abstract: An apparatus includes a charge pump array including multiple charge pump cells. The charge pump array is configurable into a first arrangement of the charge pump cells coupled in series or a second arrangement of the charge pump cells coupled in parallel. The apparatus can include reconfiguration circuitry configured to select the first arrangement of the charge pump cells or the second arrangement of the charge pump cells. The charge pump array is configured to alter a voltage level of a signal based, at least in part, on the selected arrangement of the charge pump cells.

Abstract: A circuit for generating a voltage is disclosed. The voltage has an amplitude greater than an available power supply. The circuit includes a driver to supply the voltage on an output terminal to an electrode of a touch sense array. The circuit also includes a charge pump array coupled to the driver. The charge pump array includes an array of charge pumps to supply an input voltage to the driver. The circuit also includes a feedback circuit coupled to the charge pump array. The feedback circuit is configured to measure the input voltage and to select different combinations of the array of charge pumps to maintain the voltage on the output terminal.

Abstract: An active integrator for sensing capacitance of a touch sense array is disclosed. The active integrator is configured to receive from the touch sense array a response signal having a positive portion and a negative portion. The response signal is representative of a presence or an absence of a conductive object on the touch sense array. The active integrator is configured to continuously integrate the response signal.

Abstract: An acoustic processing module receives an acoustic signal, and outputs an analog output signal. Microphone sensors are provided for generating a corresponding electrical signal in response to the acoustic signal. A signal processing circuit is connected to the microphone sensors, and processes the electrical signals according to one or more analog signal processing functions to generate the analog output signal. An integrated casing encapsulates the microphone sensors and the analog processing circuit, and prevents external interference from affecting any electrical signals within the integrated casing.

Abstract: Methods and systems for providing a programmable earphone device with customizable controls and heartbeat monitoring are described. The earphone device may include a wireless connection to a media player, a left and a right earphone, and at least one input mechanism, wherein the input mechanism is located on at least one of the left and right earphones and is customizable. The earphone device may also include an data port configured to bypass the wireless connection and receive sound data from the media player when a wired connection is detected between the media player and the earphone device. A stored customizable sound equalizer may also be included that provides different equalizer settings for each of the left and right earphones. The earphone device also includes a heartbeat monitor that detects a user's heartbeat using the left and right earphone, wherein the heartbeat monitor is customizable by the user.

Abstract: An acoustic processing module receives an acoustic signal, and outputs an analog output signal. Microphone sensors are provided for generating a corresponding electrical signal in response to the acoustic signal. A signal processing circuit is connected to the microphone sensors, and processes the electrical signals according to one or more analog signal processing functions to generate the analog output signal. An integrated casing encapsulates the microphone sensors and the analog processing circuit, and prevents external interference from affecting any electrical signals within the integrated casing.

Abstract: Power-sequencing controllers are connected to allow more complex power sequencing and/or larger numbers of voltage supplies to be monitored than with a single controller. Power-on-reset (POR) output signals from the “slave” controllers are connected by a wired-OR, and the composite output is used as a reset signal or indicator signal by the “master” controller. An output from the master controller coupled to the composite input signal is connected with the {overscore (POR)} output of the master controller by a wired-OR, and this composite signal is coupled to the reset terminals of the slave controllers. Connecting controllers in a master/slave configuration allows prevents any of the slave devices from starting until all the devices have been released, resulting in synchronous processing of subsequent signals and events.

Abstract: Systems and methods are disclosed to provide clock generation. In accordance with one embodiment, a clock generator chip is provided that is configurable and in-system programmable and includes a flexible skew control architecture. The clock generator chip may also provide programmable input circuits, programmable output circuits, and permit a JTAG boundary scan.

Abstract: Systems and methods are disclosed to provide clock generation. In accordance with one embodiment, a clock generator chip is provided that is configurable and in-system programmable. The clock generator chip may provide programmable input circuits, programmable output circuits, and permit a JTAG boundary scan.

Abstract: Device driver circuits based on H-bridges can be implemented to provide linear control of the H-bridge, reduce power losses, and reduce certain component size/cost. The driver circuits can use two feedback loops to operate the H-bridge in different regions and to guarantee that current flows through an H-bridge load device, such as a thermoelectric cooler, in only one direction at a given time. The H-bridge driver circuits can remove the possibility of high currents bypassing the load device and thus going directly through the switches on either side of the H-bridge driver. The H-bridge driver circuits also ensure careful control of the current applied to the H-bridge load device. Such driver circuits are particularly useful for controlling the current applied to thermoelectric devices.

Abstract: A programming technique for a programmable logic device (PLD) is disclosed wherein the programmed PLD controls a circuit's behavior according to a desired circuit behavior implementation. A user constructs a program, wherein the program comprises instructions defining inputs, outputs, and conditional branching for an abstract state sequencer that implements the desired circuit behavior. The programming technique then translates the states and resources for the abstract state sequencer into HDL source code, which in turn may be translated into a programming bit pattern for the PLD.

Abstract: Systems and methods are disclosed to provide clock generation. In accordance with one embodiment, a clock generator chip is provided that is configurable and in-system programmable and includes a flexible skew control architecture. The clock generator chip may also provide programmable input circuits, programmable output circuits, and permit a JTAG boundary scan.

Abstract: An output block for an in-system programmable analog integrated circuit. The output block features an output amplifier that accepts a differential current-mode input signal and provides a single-ended output voltage. The output amplifier is also selectably operable as a linear amplifier, an integrator or a comparator. The output block also includes a common-mode feedback circuit (CMFB), an analog trim circuit (OATRM), a CLAMP circuit, and an offset calibration circuit (CLDAC), all coupled to the differential input of the output amplifier. The CMFB exhibits bandwidth comparable to that of the output amplifier and a drive capability that enables the differential-input to single-ended output conversion. The CLAMP is connected to the differential input in the comparator mode in order to avoid slow recovery from an overdrive condition. The OATRM forces a difference current into the differential input that compensates for a (gain independent) offset voltage that results from various mismatches.

Abstract: Power supply sequencing systems and methods are disclosed. In one embodiment, a programmable charge pump supplies a programmable current source, which drives an external NFET that controls whether power is supplied to a device or a portion of circuitry. The maximum voltage and the turn-on ramp rate supplied to the NFET are programmable and, therefore, the NFET can be operated safely within its rated limits without requiring external protection devices. If a high-voltage output terminal is not required to drive an external NFET, the output terminal, in accordance with another embodiment, may be configured to function as an open drain logic output terminal.