Abstract: The data contents of memory systems are mostly safeguarded via an EDC method. The memory system is structured such that the recognizability of multi-bit errors is improved considerably by the EDC method.

Abstract: A memory system is disclosed wherein data contents of the memory system are protected via an EDC coding method and wherein, in order to be able to recognize addressing errors, addresses are also involved in such EDC coding.

Abstract: The data contents of memory systems are usually protected via an EDC system. When an error is present in the memory system, the EDC system can only recognize this error after the readout of faulty data.

Abstract: Method and apparatus for testing a smallest addressable unit of a storage medium of a RAM memory system for determination of a number of bit errors lying above a defined order. The test of a smallest addressable unit of a storage medium occurs completely and quickly in an optimum manner. To this end, a test procedure based on parity formation using at least first and second test patterns is used, wherein the effect of a bit error for a test pattern is transferred into the next test pattern. A combination of bit errors when checking this test pattern is thus recognized, derived from the addition of bit errors that appeared separately in the first and second test patterns.

Abstract: Data are error protected; dual memory control is utilized. From one memory control only write-in data are transmitted in addition to address and control signals; from the other memory control only control data is transmitted. In the first case they are inputted into the user data segment of a segmented memory, while in the second case, they are inputted into the control data segment of the memory from whence they are both included into the data check. Thereby, address errors may also be recognized.