Abstract: A method includes illuminating radiation to a resist layer over a substrate to pattern the resist layer. The patterned resist layer is developed by using a positive tone developer. The patterned resist layer is rinsed using a basic aqueous rinse solution. A pH value of the basic aqueous rinse solution is lower than a pH value of the developer, and a rinse temperature of rinsing the patterned resist layer is in a range of about 20° C. to about 40° C.

Abstract: A system and method for depositing a photoresist and utilizing the photoresist are provided. In an embodiment a deposition chamber is utilized along with a first precursor material comprising carbon-carbon double bonds and a second precursor material comprising repeating units to deposit the photoresist onto a substrate. The first precursor material is turned into a plasma in a remote plasma chamber prior to being introduced into the deposition chamber. The resulting photoresist comprises a carbon backbone with carbon-carbon double bonds.

Abstract: A semiconductor device is presented. The semiconductor device includes a lower semiconductor die, a stack of upper semiconductor dies disposed over the lower semiconductor die, a top semiconductor die disposed over the stack of upper semiconductor dies, a non-conductive film material disposed between adjacent semiconductor dies of the lower semiconductor die and the stack of upper semiconductor dies, and a mold compound material disposed between the top semiconductor die and the stack of upper semiconductor dies, and on sidewalls of the stack of upper semiconductor dies and the top semiconductor die.

Abstract: There is provided a capacitive touch control system adapted to detect low frequency signals, including a touch panel and an analog front end. The analog front end includes a frequency booster, which boosts a low frequency signal outputted by the touch panel using a variable reference frequency corresponding to different function symbols of the low frequency signal such that resistance of a resistor of an amplifier in the analog front end needs not to be increased thereby reducing the manufacturing cost and a leakage voltage drop on the resistor.

Abstract: A mechanical keyboard is provided, which includes a plurality of mechanical keys, a circuit board, a plurality of first magnetic elements, a lower casing and a plurality of second magnetic elements. The mechanical keyboard has a key region and an edge region surrounding the key region. The mechanical keys are located in the key region. The circuit board is disposed beneath the mechanical keys. The first magnetic elements are disposed beneath the circuit board and distributed in the key region. The lower casing is disposed beneath the mechanical keys, the circuit board and the first magnetic elements. The second magnetic elements are disposed over the lower casing, in which the second magnetic elements respectively correspond to the first magnetic elements and respectively repel the first magnetic elements.

Abstract: The present disclosure relates to a field of hollow silica nanospheres. Particularly, the present disclosure relates to silica nanoparticles as adjuvant to induce or enhance immune response or as carrier to deliver antigen to a body.

Abstract: The present disclosure relates to a method of preventing or treating brain cancers or brain metastases with mesoporous silica nanoparticles (MSNs) loaded with taxane-based chemotherapeutic drugs, in particular paclitaxel (PTX), cabazitaxel (CTX) or docetaxel (DTX), and the MSNs loaded with PTX, CTX or DTX.

Abstract: A high-electron mobility transistor includes a substrate, a gate electrode, a drain electrode, a source electrode and a first field plate. The substrate includes an active region. The gate electrode is disposed on the substrate. The drain electrode is disposed at one side of the gate electrode. The source electrode is disposed at another side of the gate electrode. The first field plate is electrically connected with the source electrode and extends from the source electrode toward the drain electrode. An overlapping area of the first field plate and the gate electrode is smaller than an overlapping area of the gate electrode and the active region.

Abstract: A pulse pressure measuring apparatus including a plurality of pressing elements, a plurality of pressure sensors, and a processing unit is provided. The pressing elements are used to press the site to be measured, and each pressing element has a position coordinate Pi (i=1, 2, 3 . . . ). The pressure sensors are configured to respectively measure pressure on the pressing elements to generate measured values of pressure intensity Ii (i=1, 2, 3 . . . ) at the position coordinates Pi (i=1, 2, 3 . . . ). The processing unit utilizes the position coordinates Pi (i=1, 2, 3 . . . ) and the measured values of pressure intensity Ii (i=1, 2, 3 . . . ) to determine the blood vessel locus.

Abstract: An interconnect structure includes a first conductive feature, a first dielectric layer a first etch stop layer, a second etch stop layer, a second dielectric layer, and a second conductive feature. The first etch stop layer is disposed over the first conductive feature and the first dielectric layer. The second etch stop layer is disposed on the first etch stop layer. The second dielectric layer is disposed on the second etch stop layer. The second conductive feature includes a first conductive layer and a first barrier layer. The first conductive layer extends through the second dielectric layer, the second and the first etch stop layers to contact to the first conductive feature. The first barrier layer is sandwiched between the first conductive layer and the second dielectric layer, the first conductive layer and the second etch stop layer, and between the first conductive layer and the first etch stop layer.

Abstract: A light emitting diode package structure and a method for manufacturing the same are provided. The LED package structure includes a substrate having a first and a second surface opposite to each other, a conductive structure including a first and a second conductive structure electrically connected with each other, a first gold layer disposed on the first conductive structure, a second gold layer disposed on the second conductive structure, an LED chip disposed on the first gold layer, and a package layer disposed on the first surface and encapsulating the first conductive structure, the first gold layer, and the LED chip. The first conductive structure is disposed on the first surface. The second conductive structure is disposed on the second surface. A thickness of the first gold layer is greater than 1 ?m. The second conductive structure is completely covered by the second gold layer.

Abstract: The fish screen for a suction strainer includes at least one first plate having a central opening formed therethrough, a second plate, a helical spring, and a mesh bag. The helical spring has opposed first and second ends, with the first end secured to the at least one first plate and the second end secured to the second plate. The helical spring has first and second portions positioned respectively adjacent to the first and second ends. The second portion has a smaller diameter than a diameter of the first portion. The mesh bag releasably and removably covers and receives the at least one first plate, the second plate and the helical spring. The second portion of the helical spring is adapted for releasably holding a free end of a suction strainer received within an interior of the helical spring through the central opening of the at least one first plate.

Abstract: A multi-configuration exercise device may include a base frame. A multi-configuration exercise device may include an interface frame. A multi-configuration exercise device may include a first cylindrical pad, such that the interface frame is manipulatable in one or more of: a height with respect to the base frame, or an orientation with respect to the base frame. In a first configuration, the first cylindrical pad is removably coupled to the interface frame. In a second configuration, the first cylindrical pad is removably coupled to the base frame.

Abstract: A continuous laser processing system for internal modification of transparent materials includes a pulse laser device, a scanning device, a processing platform and a control device. The pulse laser device is configured to output a laser beam. The scanning device includes a mirror group controller and a mirror group and controlled to guide the laser beam to the transparent material, wherein the mirror group is disposed at an output path of the laser beam. The processing platform is configured to carry the transparent material and controlled to move. The control device is electrically connected to the scanning device and the processing platform, and is configured to control the scanning device to form a processing trajectory at the transparent material at a scanning speed, and to control the processing platform to move at a translation speed, wherein the scanning speed is at least 20 times the translation speed.

Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.

Abstract: A scalable platform for generating time-frequency-multiplexed cluster states and utilizing them for large-scale quantum computing. Kerr microcombs and continuous-variable (CV) quantum information are used to formulate a one-way quantum computing architecture that can accommodate hundreds of simultaneously addressable entangled optical modes multiplexed in the frequency domain and an unlimited number of sequentially addressable entangled optical modes in time domain. One-dimensional, two-dimensional, and three-dimensional CV cluster states can be deterministically produced using robust integrated photonic circuit technology is leveraged that is readily available and experimentally viable.

Abstract: A circuit board structure is provided. The circuit board structure includes a substrate, a solder mask coupler, a supporter, and a chip. The substrate has a conductive structure. The solder mask coupler is disposed on the substrate. The supporter contacts the solder mask coupler, and the supporter is fixed on the substrate via the solder mask coupler. The chip is disposed on the substrate, and the chip is electrically connected with the conductive structure.

Abstract: A method and system is provided in a simulation platform for optimizing the extrinsic parameters of fisheye-lens cameras installed on a vehicle. A simulated vehicle is established according to vehicular characteristics of associated actual vehicle over the simulated platform, thereby a lot of simulated checkerboard calibration plates are placed surrounding the simulated vehicle. A lot of simulated fisheye-lens cameras are generated and mounted on the simulated vehicle based on intrinsic parameters associated with actual fisheye lenses, and fisheye images are derived by using the simulated fisheye-lens cameras, respectively. The initially extrinsic parameters of each of the simulated fisheye-lens cameras are calculated over the simulated platform by using the first characteristic points of its own first fisheye image.

Abstract: A method for forming a semiconductor structure includes following operations. A first metallization feature is formed, and a first cap layer is formed over the first metallization feature. A first insulating layer is formed over the first cap layer and the first metallization feature. A first dielectric structure is formed over the first insulating layer. A portion of the first dielectric structure and a portion of the first insulating layer are removed to expose the first cap layer. A second cap layer is formed over the first cap layer and the first metallization feature. A second insulating layer and a patterned second dielectric structure are formed over the substrate. The patterned second dielectric structure includes a trench and a via opening coupled to a bottom of the trench. A second metallization feature is formed in the trench, and a via structure is formed in the via opening.