Abstract: A method and apparatus is disclosed for minimizing power virus in a network on chip. The method includes an operational metric related to a node with at least one threshold, the node configured to manage communication of a first number of outbound transactions; determining, based on the comparison, a second number of outbound transactions from the first number of outbound transactions that are allowed from the node; and communicating the second number of outbound transactions. An apparatus for minimizing power virus in a network on chip is also disclosed.

Abstract: Aspects of the present disclosure propose techniques for testing a network on chip (NoC). An exemplary method may generally include generating, at a source node of the NoC, a first plurality of packets according to a first pre-defined pattern of a plurality of pre-defined patterns, wherein each pre-defined pattern is designed to provoke transients in the NoC, generating, at the source node of the NoC, a second plurality of packets according to the first pre-defined pattern of the plurality of pre-defined patterns, generating the transients in the NoC by transmitting the first plurality of packets and thereafter transmitting the second plurality of packets, and verifying at least one of the first plurality of packets or the second plurality of packets are successfully received at a destination node of the NoC despite the generated transients.