Abstract: A method and apparatus provides a service based on biometric information. A bioelectrical impedance of a user is measured at a first time point to obtain a first value representing biometric information of the user. At least one processor predicts the biometric information of the user at a third time point subsequent to the first time point to obtain a third value, based on the first value representing biometric information of the user at the first time point and a second value representing the biometric information at a second time point prior to the first time point. The processor calculates a difference between a fourth value representing a target related to the biometric information of the user, input by the user in advance, and the third value. Information regarding a health management service is output based on the difference between the fourth value and the third value.

Abstract: A method of manufacturing an IC includes detecting connectivity between polygons from layout data of the IC and extracting a layout netlist, by performing a DRC on the layout data. The DRC includes loading a rule file including a DRC syntax. The method includes performing LVS verification on the extracted layout netlist and schematic data of the IC to generate LVS result data. The method includes manufacturing the IC according to a layout based on the layout data and the LVS result data.

Abstract: A method of manufacturing an IC includes detecting connectivity between polygons from layout data of the IC and extracting a layout netlist, by performing a DRC on the layout data. The DRC includes loading a rule file including a DRC syntax. The method includes performing INS verification on the extracted layout netlist and schematic data of the IC to generate LVS result data. The method includes manufacturing the IC according to a layout based on the layout data and the LVS result data.

Abstract: A method ana apparatus provides a service based on biometric information. A bioeiectrical impedance of a user is measured at a first time point to obtain a first value representing biometric information of the user. At least one processor predicts the biometric information of the user at a third time point, subsequent to the first time point to obtain a third value, based on the first value representing biometric information of the user at the first time point and a second value representing the biometric information at a second time point prior to the first time point. The processor calculates a difference between a fourth value representing a target related to the biometric information of the user, input by the user in advance, and the third value. Information regarding a health management service is output based on the difference between the fourth value and the third value.

Abstract: A device for measuring biometric information includes an impedance measurement circuit, a storage circuit, and a control circuit. The impedance measurement circuit receives an electrical signal from a plurality of electrodes when the plurality of electrodes are in contact with a body of a user and measures a bioelectrical impedance using the electrical signal. The storage circuit includes a security area configured to store the bioelectrical impedance, body information of the user, and biometric information of the user obtained from the bioelectrical impedance and the body information. The control circuit includes an authentication means configured to determine access authority to data stored in the security area using an authentication procedure, obtains the biometric information from the bioelectrical impedance and the body information, and manages the security area through the authentication procedure provided by the authentication means.

Abstract: A memory device capable of performing an overwrite operation, a memory system, and a method of operating the memory system are provided. The method includes receiving one or more write requests, a logical address and data corresponding to the one or more write requests; comparing a result of analyzing at least one of the received one or more write requests, logical address, and data with a threshold value; and writing data using a first update method or a second update method, based on a result of the comparison. When the first update method is selected, the data are written in a region indicated by a physical address corresponding to the logical address according to address mapping information. When the second update method is selected, information of the physical address corresponding to the logical address is changed, and the data are written in a region indicated by the changed physical address.

Abstract: A storage device is provided. The storage device includes storage clusters, and a controller. The controller receives a command and an address from an external host device, selects a storage cluster according to the received address, and transmits the received command and the received address to the selected storage cluster. The controller controls the storage clusters as normal storage clusters and slow storage clusters according to a temperature of a zone to which the storage clusters belong.

Abstract: A method is for operating a resistive memory system including a resistive memory device implemented as multi-level memory cells. The method includes setting levels of reference voltages used to determine resistance states of the multi-level memory cells, and reading data of the multi-level memory cells based on the reference voltages. A difference between the reference voltages used to determine a relatively high resistance state is greater than a difference between the reference voltages used to determine a relatively low resistance state.

Abstract: A resistive memory system having a plurality of memory cells includes a memory device having a resistive memory cell array and a controller. The controller generates write data to be written to the memory cell array by encoding input data such that the input data corresponds to an erase state and a plurality of programming states that a memory cell may have. The input data is encoded such that at least one of the number of memory cells assigned a first programming state and the number of memory cells assigned a second programming state is smaller than at least one of the numbers of memory cells in the erase state and the other programming states. The first programming state has a highest resistance level among the plurality of programming states, and the second programming state has a second highest resistance level among the plurality of programming states.

Abstract: A storage device is provided. The storage device includes storage clusters, and a controller. The controller receives a command and an address from an external host device, selects a storage cluster according to the received address, and transmits the received command and the received address to the selected storage cluster. The controller controls the storage clusters as normal storage clusters and slow storage clusters according to a temperature of a zone to which the storage clusters belong.

Abstract: A method is for operating a resistive memory system including a resistive memory device implemented as multi-level memory cells. The method includes setting levels of reference voltages used to determine resistance states of the multi-level memory cells, and reading data of the multi-level memory cells based on the reference voltages. A difference between the reference voltages used to determine a relatively high resistance state is greater than a difference between the reference voltages used to determine a relatively low resistance state.

Abstract: A resistive memory system having a plurality of memory cells includes a memory device having a resistive memory cell array and a controller. The controller generates write data to be written to the memory cell array by encoding input data such that the input data corresponds to an erase state and a plurality of programming states that a memory cell may have. The input data is encoded such that at least one of the number of memory cells assigned a first programming state and the number of memory cells assigned a second programming state is smaller than at least one of the numbers of memory cells in the erase state and the other programming states. The first programming state has a highest resistance level among the plurality of programming states, and the second programming state has a second highest resistance level among the plurality of programming states.

Abstract: A memory device capable of performing an overwrite operation, a memory system, and a method of operating the memory system are provided. The method includes receiving one or more write requests, a logical address and data corresponding to the one or more write requests; comparing a result of analyzing at least one of the received one or more write requests, logical address, and data with a threshold value; and writing data using a first update method or a second update method, based on a result of the comparison. When the first update method is selected, the data are written in a region indicated by a physical address corresponding to the logical address according to address mapping information. When the second update method is selected, information of the physical address corresponding to the logical address is changed, and the data are written in a region indicated by the changed physical address.