Patents by Inventor Hanumantha Raya

Hanumantha Raya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8677196
    Abstract: Embodiments provide methods, systems, devices, and/or machine readable storage medium for memory built-in self testing (memory BIST) that may not require JTAG. Embodiments may provide less chip overhead through the use of one or more direct access pins. Embodiments may provide simple checks to determine if the memories on a chip are good or bad with minimal cost, for example. In some cases, the memory BIST may determine whether or not memories are good when the chip powers on. Some embodiments may also perform stress testing on the memories to force early life failures of the memories. Embodiments do not necessarily have to diagnose failures.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: March 18, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Steven Lee Gregor, Norman Robert Card, Hanumantha Raya, Puneet Arora