Abstract: Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal based on an XOR-based function of data input and data output-based signals of a pulse latch. A pull-down keeper circuit is configured to pull the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state while the clock signal is in an active state. A logic circuit is configured to generate an adaptive pulse signal to clock a pulse latch in response to the pulse generation signal and the clock signal being in an active state. This configuration results in the pulse width of the adaptive pulse signal corresponding to the input-to-output delay of the pulse latch.

Abstract: Provided is a local bit line-sharing memory device, including a plurality of memory cells that share a local bit line pair; a pre-charging unit that is connected to a write bit line pair and pre-charges the local bit line pair; and a data reading unit that reads data when bit line voltage pre-charged in a memory cell selected from the memory cells is discharged.

Abstract: Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal based on an XOR-based function of data input and data output-based signals of a pulse latch. A pull-down keeper circuit is configured to pull the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state while the clock signal is in an active state. A logic circuit is configured to generate an adaptive pulse signal to clock a pulse latch in response to the pulse generation signal and the clock signal being in an active state. This configuration results in the pulse width of the adaptive pulse signal corresponding to the input-to-output delay of the pulse latch.

Abstract: Disclosed is a local bit line-sharing memory device, including a plurality of memory cells that share a local bit line pair; a pre-charging unit that is connected to a write bit line pair and pre-charges the local bit line pair; and a data reading unit that reads data when bit line voltage pre-charged in a memory cell selected from the memory cells is discharged.

Abstract: The present disclosure herein relates to a sense amplifier and a semiconductor memory device employing the same. The sense amplifier includes an inverter including a pull-up transistor and a pull-down transistor, and a switching unit configured to change a connection relationship between the pull-up transistor and the pull-down transistor according to whether an input terminal of the inverter is precharged or a signal applied to the input terminal is sensed.

Abstract: Disclosed is a memory device. The memory device includes a bit-cell comprising a cross-coupled inverter and pass gate transistor connected to data storage node of the cross-coupled inverter, a read buffer transistor having a drain terminal connected to a bit line for read operation and a gate terminal connected to the pass gate transistor, a write operation transistor connected between the pass gate transistor and a bit line for write operation, and a drive transistor unit which is connected to a local line between the pass gate transistors and the write operation transistor and which provide a voltage to a gate terminal of the read buffer transistor based on a data value stored at the bit-cell.

Abstract: A static random access memory device may include a write driver configured to float one of a first bitline and a second bitline connected to a memory cell and apply a write voltage to the other bitline in response to a logic state of a data signal; a write failure detector configured to receive a voltage of the floated bitline and output a write failure signal; and an assist voltage generator configured to generate a write assist voltage in response to the write failure signal. The write driver may additionally provide the write assist voltage to a bitline to which the write voltage is applied.

Abstract: The present disclosure herein relates to a sense amplifier and a semiconductor memory device employing the same. The sense amplifier includes an inverter including a pull-up transistor and a pull-down transistor, and a switching unit configured to change a connection relationship between the pull-up transistor and the pull-down transistor according to whether an input terminal of the inverter is precharged or a signal applied to the input terminal is sensed.

Abstract: Disclosed is a memory device. The memory device includes a bit-cell comprising a cross-coupled inverter and pass gate transistor connected to data storage node of the cross-coupled inverter, a read buffer transistor having a drain terminal connected to a bit line for read operation and a gate terminal connected to the pass gate transistor, a write operation transistor connected between the pass gate transistor and a bit line for write operation, and a drive transistor unit which is connected to a local line between the pass gate transistors and the write operation transistor and which provide a voltage to a gate terminal of the read buffer transistor based on a data value stored at the bit-cell.

Abstract: A static random access memory device may include a write driver configured to float one of a first bitline and a second bitline connected to a memory cell and apply a write voltage to the other bitline in response to a logic state of a data signal; a write failure detector configured to receive a voltage of the floated bitline and output a write failure signal; and an assist voltage generator configured to generate a write assist voltage in response to the write failure signal. The write driver may additionally provide the write assist voltage to a bitline to which the write voltage is applied.