Abstract: A user equipment device intelligent network selection architecture is provided that enables service provider policy driven dynamic intelligent network selection of a radio technology for user traffic delivery. The network selection is based on radio network conditions, user subscription profile, and device mobility state, including speed and movement pattern. Also provided are application program interfaces that allow access network discovery and selection function carrier clients decision as to communication with a connection manager or other lower layer functions. The architecture and associated application program interface enable automatic network selection and connection, which provides a consistent implementation across different device original equipment manufacturers and operating systems.

Abstract: A user equipment device intelligent network selection architecture is provided that enables service provider policy driven dynamic intelligent network selection of a radio technology for user traffic delivery. The network selection is based on radio network conditions, user subscription profile, and device mobility state, including speed and movement pattern. Also provided are application program interfaces that allow access network discovery and selection function carrier clients decision as to communication with a connection manager or other lower layer functions. The architecture and associated application program interface enable automatic network selection and connection, which provides a consistent implementation across different device original equipment manufacturers and operating systems.

Abstract: An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use of the input and the memory array and calibrate the on die termination circuitry with the resistor coupled to the reference voltage. Other embodiments are disclosed herein.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for per byte lane dynamic on-die termination. In some embodiments, an integrated circuit includes logic to independently program at least one on-die termination (ODT) value for each of a plurality of integrated circuits coupled together through an interconnect. Other embodiments are described and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pin to receive one or more ODT signals. The integrated circuit may further include control logic coupled to the ODT pin, the control logic to enable, at least in part, a multiplexing of an ODT activation signal and an ODT value selection signal on the ODT pin, the control logic further to control a length of termination based, at least in part, on the command. Other embodiments are described and claimed.

Abstract: The termination impedance of a memory agent may be selected dynamically. A transmission line may be simultaneously terminated with a first impedance at first memory agent and a different impedance at a second memory agent. A memory agent may have a terminator with at least two termination values and logic to dynamically select the termination values. Other embodiments are described and claimed.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pin to receive one or more ODT signals. The integrated circuit may further include control logic coupled to the ODT pin, the control logic to enable, at least in part, a multiplexing of an ODT activation signal and an ODT value selection signal on the ODT pin, the control logic further to control a length of termination based, at least in part, on the command. Other embodiments are described and claimed.

Abstract: An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use of the input and the memory array and calibrate the on die termination circuitry with the resistor coupled to the reference voltage. Other embodiments are disclosed herein.

Abstract: A technique is discussed for a different memory sub system topology to allow for separating impedance discontinuity The trace lengths from the MCH and the trace lengths to each memory device is calculated based at least in part on a frequency domain and time domain analysis. The new topology improves the impedance discontinuity that was evident in the P22P topology.

Abstract: Apparatus and method for producing memory modules having a plurality of dynamic random access memory (DRAM) devices or synchronous random access memory (SDRAM) devices connected to a memory bus, each DRAM or SDRAM device connected to the memory bus via a transmission signal (TS) line. The memory bus includes at least one TS line having a capacitor connected to the TS line in parallel to the plurality of DRAM or SDRAM devices, the TS line connected to the memory bus between a signal insertion end and an attachment point of a TS line of a first DRAM or SDRAM device. A computing system implementing the memory modules is also discussed.

Abstract: A memory interface and a method to interface with high-speed memory devices have been disclosed. One embodiment of the memory interface includes an inductor and a number of transmission lines. The transmission lines are coupled to the inductor in series to couple a number of memory devices to a circuit board.