Abstract: Apparatus and method for producing memory modules having a plurality of dynamic random access memory (DRAM) devices or synchronous random access memory (SDRAM) devices connected to a memory bus, each DRAM or SDRAM device connected to the memory bus via a transmission signal (TS) line. The memory bus includes at least one TS line having a capacitor connected to the TS line in parallel to the plurality of DRAM or SDRAM devices, the TS line connected to the memory bus between a signal insertion end and an attachment point of a TS line of a first DRAM or SDRAM device. A computing system implementing the memory modules is also discussed.

Abstract: A memory interface and a method to interface with high-speed memory devices have been disclosed. One embodiment of the memory interface includes an inductor and a number of transmission lines. The transmission lines are coupled to the inductor in series to couple a number of memory devices to a circuit board.

Abstract: Briefly, in accordance with one embodiment of the invention, a system includes two boards coupled by a bus. The bus having a dual-terminated transmission line that communicatively couples a memory control hub with a memory repeater hub that each have a Rambus ASIC Cell (RAC). Briefly, in accordance with another embodiment of the invention, a connector has two metal traces that are of different lengths. The parasitic capacitance of the longer metal trace is increased so that the impedance of the two metal traces is substantially equal.

Abstract: According to some embodiments, a voltage plane with a high impedance link is provided. For example, the high impedance link might be a meandered conducting neck between a first low impedance voltage plane portion and a second low impedance voltage plane portion. As other examples, the high impedance link might be a stepped impedance filter or a slotted around filter.

Abstract: According to some embodiments, a voltage plane with a high impedance link is provided.