Abstract: An integrated circuit device includes a pair of fin-type active regions collinear with each other on a substrate, a gate line disposed on one of the fin-type active regions, a capping insulating layer that covers the gate line, and a fin isolation insulating portion that passes through the capping insulating layer in a vertical direction between the pair of fin-type active regions. The fin isolation insulating portion includes an isolation insulating plug that includes a first portion disposed between the pair of fin-type active regions and a second portion integrally connected to the first portion and that passes through the capping insulating layer in the vertical direction, and an isolation insulating liner that surrounds a bottom surface and a sidewall of the isolation insulating plug. The isolation insulating liner includes an uppermost portion that is closer to the substrate than a top surface of the isolation insulating plug.

Abstract: An integrated circuit device includes a first fin-type active region and a second fin-type active region extending in a first lateral direction on a substrate, a first gate line extending in a second lateral direction intersecting the first lateral direction on the first fin-type active region, a second gate line apart from the first gate line in the second lateral direction on the second fin-type active region and extending along an extension line of the first gate line in the second lateral direction, and a gate cut insulating pattern between the first gate line and the second gate line, wherein, for at least one of the first gate line and the second gate line, a width of a terminal gate portion, which is adjacent to the gate cut insulating pattern, in the first lateral direction is less than a width of another portion in the first lateral direction.