Patents by Inventor Hao Chang Chen
Hao Chang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12002906Abstract: The present disclosure provides a semiconductor device and a semiconductor component. The semiconductor device includes an active structure, a ring-shaped semiconductor contact layer, a first electrode, and an insulating layer. The active structure has a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer located between the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer. The ring-shaped semiconductor contact layer is located on the second-conductivity-type semiconductor layer and having a first inner sidewall and a first outer sidewall. The first electrode has an upper surface and covers the ring-shaped semiconductor contact layer. The insulating layer covers the first electrode and the active structure and has a second inner sidewall and a second outer sidewall. The first inner sidewall is not flush with the second inner sidewall in a vertical direction.Type: GrantFiled: August 19, 2021Date of Patent: June 4, 2024Assignee: EPISTAR CORPORATIONInventors: Hao-Chun Liang, Wei-Shan Yeoh, Yao-Ning Chan, Yi-Ming Chen, Shih-Chang Lee
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Patent number: 11963300Abstract: A panel device including a substrate, a conductor pad, a turning wire, and a circuit board is provided. The substrate has a first surface and a second surface connected to the first surface while a normal direction of the second surface is different from a normal direction of the first surface. The conductor pad is disposed on the first surface of the substrate. The turning wire is disposed on the substrate and extends from the first surface to the second surface. The turning wire includes a wiring layer in contact with the conductor pad and a wire covering layer covering the wiring layer. The circuit board is bonded to and electrically connected to the wire covering layer. A manufacturing method of a panel device is also provided herein.Type: GrantFiled: July 9, 2021Date of Patent: April 16, 2024Assignee: Au Optronics CorporationInventors: Chun-Yueh Hou, Hao-An Chuang, Fan-Yu Chen, Hsi-Hung Chen, Yun Cheng, Wen-Chang Hsieh, Chih-Wen Lu
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Patent number: 11946569Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.Type: GrantFiled: April 19, 2021Date of Patent: April 2, 2024Assignee: MICROJET TECHNOLOGY CO., LTD.Inventors: Hao-Jan Mou, Shih-Chang Chen, Jia-Yu Liao, Hung-Hsin Liao, Chung-Wei Kao, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee
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Publication number: 20240071888Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.Type: ApplicationFiled: August 28, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chang Lin, Yen-Fu Su, Chin-Liang Chen, Wei-Yu Chen, Hsin-Yu Pan, Yu-Min Liang, Hao-Cheng Hou, Chi-Yang Yu
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Patent number: 7714932Abstract: An apparatus for adaptive de-interlace of a frame comprises a line-segment difference-value calculating module, a motion-vector calculating module, an intra-block calculating module, a trigger-value producing module, and an image processing module. The line-segment difference-value calculating module computes a difference value of a line segment within the frame. The motion-vector calculating module computes a motion vector of a macro block that is located in the frame and comprises the line segment. The intra-block calculating module computes the amount of intra blocks in the frame. The trigger-value producing module determines whether the amount of the intra blocks is larger than a first threshold or not, so as to select an algorithm for generating a trigger value. The image processing module determines whether the trigger value is larger than a second threshold or not and then selects a de-interlace algorithm for de-interlacing the line segment.Type: GrantFiled: March 7, 2008Date of Patent: May 11, 2010Assignee: Via Technologies, Inc.Inventors: Hao Chang Chen, Sheng-Che Tsao
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Patent number: 7423692Abstract: A de-interlace method and method for generating a de-interlace algorithm include steps of generating an adaptive tuning de-interlace algorithm. The steps of the method for generating a de-interlace algorithm include generating a characteristic difference value according to a first line-segment data and a second line-segment data, determining a blending vector based on the characteristic difference value, and generating the adaptive tuning de-interlace algorithm according to the blending vector Wherein, the blending vector is to determine a weight of a first de-interlace algorithm in the adaptive tuning de-interlace algorithm, and a difference between the blending vector and a constant is to determine a weight of a second de-interlace algorithm in the adaptive tuning de-interlace algorithm. Moreover, the de-interlace method performs the adaptive tuning de-interlace algorithm to generate a de-interlaced image.Type: GrantFiled: December 1, 2004Date of Patent: September 9, 2008Assignee: Via Technologies, Inc.Inventor: Hao Chang Chen
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Publication number: 20080158418Abstract: An apparatus for adaptive de-interlace of a frame comprises a line-segment difference-value calculating module, a motion-vector calculating module, an intra-block calculating module, a trigger-value producing module, and an image processing module. The line-segment difference-value calculating module computes a difference value of a line segment within the frame. The motion-vector calculating module computes a motion vector of a macro block that is located in the frame and comprises the line segment. The intra-block calculating module computes the amount of intra blocks in the frame. The trigger-value producing module determines whether the amount of the intra blocks is larger than a first threshold or not, so as to select an algorithm for generating a trigger value. The image processing module determines whether the trigger value is larger than a second threshold or not and then selects a de-interlace algorithm for de-interlacing the line segment.Type: ApplicationFiled: March 7, 2008Publication date: July 3, 2008Inventors: Hao Chang Chen, Sheng-Che Tsao
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Patent number: 7365795Abstract: An apparatus for adaptive de-interlace of a frame comprises a line-segment difference-value calculating module, a motion-vector calculating module, an intra-block calculating module, a trigger-value producing module, and an image processing module. The line-segment difference-value calculating module computes a difference value of a line segment within the frame. The motion-vector calculating module computes a motion vector of a macro block that is located in the frame and comprises the line segment. The intra-block calculating module computes the amount of intra blocks in the frame. The trigger-value producing module determines whether the amount of the intra blocks is larger than a first threshold or not, so as to select an algorithm for generating a trigger value. The image processing module determines whether the trigger value is larger than a second threshold or not and then selects a de-interlace algorithm for de-interlacing the line segment.Type: GrantFiled: March 29, 2005Date of Patent: April 29, 2008Assignee: Via Technologies, Inc.Inventors: Hao Chang Chen, Sheng-Che Tsao