Abstract: A liquid crystal display panel includes a display area. The display area includes a first scanning line, two second scanning lines, and a number of pixel units arranged in two rows and a number of columns. The number of columns include a number of first columns and a number of second columns arranged alternately. The pixel units arranged in the number of first columns are controlled via the first scanning line, and the two pixel units arranged in each of the number of second columns are controlled via the two second scanning lines correspondingly.

Abstract: A surface contact card latching assembly (100) is located in a portable electronic device (200). The latching assembly includes a receiving portion (11) and a latch portion (12). The receiving portion is configured for receiving a surface contact card (20). The receiving portion includes an aperture (113) formed at a first end thereof via which the surface contact card enters or exits, and a latching containing portion (114) formed at an opposite second end thereof. The latch portion is received in the latching containing portion. The latch portion is operable to move in the latching containing portion so as to drive the surface contact card to move out of the receiving portion through the aperture.

Abstract: A battery cover assembly for coupling to a housing of an electronic device, the battery cover assembly comprising: a cover (10) comprising an inner surface (106) and a button slot (101) defined therein; a movable member (20) comprising a main body (21), a button (211) formed on the main body and extending through the button slot, and a catch assembly extending from the main body; and a fixing plate (30) coupled to the cover, with the movable member being sandwiched between the fixing plate and the cover, the fixing plate defining at least one opening, the catch assembly of the movable member extending through the opening and being adapted for engageably securing the cover assembly to the housing (40). The battery cover assembly has a steady structure. The battery cover assembly is convenient to open and close.

Abstract: A method of searching for the key semiconductor operation with randomization for wafer position, comprising: recording the wafer position and the wafer yields of a plurality of wafer ID respectively corresponding to a plurality of semiconductor operations; establishing a matrix model which describes the matrix set for wafer yields of the plurality of wafer ID; analyzing the matrix model, further computing the matrix set for wafer yields of the wafer ID, thereby acquiring the weightings of the randomized wafer positions in such semiconductor operations; and searching for a key semiconductor operation among the plurality of semiconductor operations; herein, by using a local regression model to estimate the wafer position effect, computing the weighting of the position effect in each semiconductor operation based on the estimated position effect and the randomized wafer yield, higher weighting thereof indicates the key semiconductor operation having greater position effect in the aforementioned semiconductor pro

Abstract: An electrical connector assembly comprises a stiffener including a base with a first portion and a second portion, insulative housing, a load plate and a lever. An embossed portion is formed on the base and has substantial distance to a first end of the first portion. An insulative housing is disposed between the first portion and the second portion. A load plate is pivotally mounted on the second portion of the stiffener. A lever is pivotally assembled to the first portion of the stiffener to lock the load plate and includes a retaining portion adjacent to the embossed portion to abut against the lever when it is rotated.

Abstract: A network authorization method is disclosed. The network authorization method includes the following steps. After a third server receives a client account from a client, the third server generates and replies a client session ID to the client. Transmit the client session ID to the client. After the client transmits a log-in session ID to a service server, receive the log-in session ID from the service server. Compare the client session ID with the log-in session ID. When the client session ID is the same with the log-in session ID, transmit an authorized signal to the service server to make the service server allow the client to log in.

Abstract: A page buffer used in a NAND flash memory comprises a first latch circuit, a second latch circuit, a bit line voltage supply circuit and a verification circuit comprising a first verification path, a second verification path and a third verification path. The first latch circuit and the second latch circuit latch the data programmed into and read from the NAND flash memory. The bit line voltage supply circuit supplies bit line voltages to the corresponding bit line of the NAND flash memory. The verification circuit verifies the programming operations of the NAND flash memory. The first verification path is for the verification of a first LSB programming operation. The second verification path is for the verification of a second LSB programming operation before the first LSB programming operation is verified. The third verification path is for the verification of the second LSB programming operation after the first LSB programming operation is verified.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a substrate having a first region and a second region, forming first and second gate stacks in the first and second regions, respectively, the first gate stack including a first dummy gate and the second gate stack including a second dummy gate, removing the first dummy gate in the first gate stack thereby forming a first trench and removing the second dummy gate in the second gate stack thereby forming a second trench, forming a first metal layer in the first trench and in the second trench, removing at least a portion of the first metal layer in the first trench, forming a second metal layer in the remainder of the first trench and in the remainder of the second trench, reflowing the second metal layer, and performing a chemical mechanical polishing (CMP).

Abstract: A network communication method comprises the following steps: a log-in account is acquired from a client; a server list is queried to obtain on-line data of a local server according to the login account, wherein the local server and the client are in the same domain; the client is directed to the local server according to the on-line data of the local server. Moreover, a dispatch server and a server are disclosed in specification.

Abstract: An improved structure of automatic pressure adjustable air bed mainly includes an air mattress, an air pump, and air pipes arranged therebetween, as well as a control system disposed on the air bed. The control system includes multiple pressure sensors disposed on the air mattress for acquiring pressure signals, and a main control unit for controlling actions of the air pump or electrical controlled valves thereon, thereby achieving the automatic adjustment of firmness of the air mattress.

Abstract: Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.

Abstract: A power regulator for converting an input voltage to an output voltage includes a pass device and an error amplifier. The pass device receives the input voltage and provides the output voltage at an output terminal of the power regulator. The error amplifier coupled to the pass device includes a transistor. The transistor receives a reference signal and a feedback signal indicative of the output voltage, compares the feedback signal to the reference signal, and generates a control signal according to a result of the comparison to drive the pass device.

Abstract: An apparatus and method for direct analysis of continuous-flow liquid samples by desorption electrospray ionization-mass spectrometry (DESI-MS) including a sample stage that is adapted to receive a liquid sample and a nebulizing ionizer that is configured to generate a charged, nebulized solvent and thereby desorb at least a portion of the liquid sample from the sample stage.

Abstract: An IC socket for receiving an IC package comprises a socket body for carrying the IC package. A plurality of contacts are received in the socket body for electrical connection with the IC package. A driving member is mounted upon the socket body and able to operate between an upper position and a lower position. At least one latch device comprises an upper section, a lower section parallel to the upper section and a regulator. The regular links the upper section and the lower section and force the lower section to move relative to the upper section.

Abstract: A contact for a burn-in socket electrically connecting an IC package and a printed circuit board, comprises a first contact, a second contact and a spring disposed between the first contact and the second contact. The first contact and the second contacts have a same configuration, and each contact has a U-shaped actuating portion with two legs and a conductive portion extending from one of the legs. The first contact and the second contact are orthogonally assembled together, and the first actuating portion bestrides the second actuating portion to clasp with second actuating portion, so that the conductive portions have an offset therebetween.

Abstract: An electrical connector (100) for electrically connecting a Central Processing Unit (CPU) with a Printed Circuit Board (PCB), includes a base (2), a plurality of insulative layers (34), a plurality of contacts (4) and a plurality of cams (33). The base defines a cavity (21) and the insulative layers are stacked and received in the cavity. The insulative layers define a plurality of passageways therein. The contacts are received in the passageways of the insulative layers. The cams are rotatable around to push different insulative layers to have different degrees of movement in a predetermined direction.

Abstract: A surface plasmon resonance meter is provided, including a backlight module, a line-slot plate, a parabolic mirror, a linear polarizer, a sensing chip, a prism and a photo detector array. The line-slot plate includes a light outlet. A light beam travels in the backlight module, and leaves the backlight module through the light outlet. The position of the line-slot plate is matched on a predetermined focal point of the parabolic mirror. The light beam is reflected by the parabolic mirror to be a parallel light beam, and travels trough the linear polarizer to the prism. The prism includes a light entering surface, a detection surface and a light exiting surface. The light beam enters the prism through the light entering surface, contacts the sensing chip with total internal reflection, and finally leaves the prism through the light exiting surface to be received by the photo detector array.

Abstract: The present invention discloses a PCI Express interface compatible with USB interface comprising a power supply terminal and a ground terminal, in which four data terminals include two data transmitting terminals and two data receiving terminals, characterized in that the power supply terminal and the ground terminal of said interface coincide with the corresponding terminals of USB interface specification, two of said four data terminals are guaranteed to have their positions and widths overlaid with the position of terminal D+ in USB interface specification and not with the position of terminal D? in USB interface specification, and the other two data terminals are guaranteed to have their positions and widths overlaid with the position of terminal D? in USB interface specification and not with the position of terminal D+ in USB interface specification.

Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a transistor formed in the substrate, the transistor including a high-k gate dielectric formed over the substrate, the high-k gate dielectric having a first length measured from one sidewall to the other sidewall of the high-k gate dielectric, and a metal gate formed over the high-k gate dielectric, the metal gate having a second length measured from one sidewall to the other sidewall of the metal gate, the second length being smaller than the first length.