Abstract: A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

Abstract: A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

Abstract: The present invention discloses a low-noise single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the electrically-conductive gate of the transistor and the electrically-conductive gate of the capacitor structure are interconnected to form a single floating gate of a memory cell; an ion-doped buried layer is formed between the dielectric layer of the capacitor structure and the semiconductor substrate to reduce the external interference on the capacitor structure and control the initial threshold voltage; a reverse bias may be used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of the low-noise single-gate non-volatile memory having an isolation well, positive and negative voltages may be applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer, and thereby, the absolute voltage, the area of th

Abstract: A single-gate non-volatile memory and an operation method thereof, wherein a transistor and a capacitor structure are embedded in a semiconductor substrate; the transistor comprises: a first electrically-conductive gate, a first dielectric layer, and multiple ion-doped regions; the capacitor structure comprises: a second electrically-conductive gate, a second dielectric layer, and a second on-doped region; the first electrically-conductive gate and the second electrically-conductive gate are interconnected to form a single floating gate of a memory cell; a reverse bias is used to implement the reading, writing, and erasing operations of the single-floating-gate memory cell; in the operation of a single-gate non-volatile memory with an isolation well, positive and negative voltages are applied to the drain, the gate, and the silicon substrate/the isolation well to create an inversion layer so that the absolute voltage, the area of the voltage booster circuit, and the current consumption can be reduced.

Abstract: A non-volatile memory structure and a method for operating the same are proposed. The non-volatile memory structure makes use of a single floating gate structure and a capacitor structure including a pair of regions doped with different type impurities to increase the capacitance and shrink the area. When performing programming operations to this memory structure, a voltage is applied to the source or a back bias is applied to the substrate of the transistor to greatly reduce the current requirement of a single-gate EEPROM device. When performing erase operations, the drain voltage is raised, and a small voltage is added to the gate to increase the F-N tunneling current, thereby accomplishing the effect of fast erase.