Patents by Inventor Hao-Cheng Hou
Hao-Cheng Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250125224Abstract: In an embodiment, a device includes: an interposer including: a back-side redistribution structure; an interconnection die over the back-side redistribution structure, the interconnection die including a substrate, a through-substrate via protruding from the substrate, and an isolation layer around the through-substrate via; a first encapsulant around the interconnection die, a surface of the first encapsulant being substantially coplanar with a surface of the isolation layer and a surface of the through-substrate via; and a front-side redistribution structure over the first encapsulant, the front-side redistribution structure including a first conductive via that physically contacts the through-substrate via, the isolation layer separating the first conductive via from the substrate.Type: ApplicationFiled: February 15, 2024Publication date: April 17, 2025Inventors: Yao-Cheng Wu, Hua-Kai Lin, Hao-Cheng Hou, Tsung-Ding Wang, Hao-Yi Tsai
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Publication number: 20240387386Abstract: An embodiment interposer may include a plurality of first redistribution layers including first electrical interconnect structures having a first line width and a first line spacing embedded in a first dielectric material, and a plurality of second redistribution layers including second electrical interconnect structures having a second line width and a second line spacing embedded in a second dielectric material such that the second line width is greater than the first line width and such that the second line spacing is greater than the first line spacing. The first dielectric material may be one of polyimide, benzocyclobuten, or polybenzo-bisoxazole and second dielectric material may include an inorganic particulate material dispersed in an epoxy resin. The interposer may further include a protective layer, including the second dielectric material, formed over the first redistribution layers, and a surface layer, including the first dielectric material, formed as part of the second redistribution layers.Type: ApplicationFiled: May 15, 2023Publication date: November 21, 2024Inventors: Shang-Yun Hou, Chien-Hsun Lee, Tsung-Ding Wang, Hao-Cheng Hou
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Publication number: 20240379535Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.Type: ApplicationFiled: July 22, 2024Publication date: November 14, 2024Inventors: Chung-Shi Liu, Chien-Hsun Lee, Jiun Yi Wu, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Li-Wei Chou
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Patent number: 12142560Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.Type: GrantFiled: August 23, 2021Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chung-Shi Liu, Chien-Hsun Lee, Jiun Yi Wu, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Li-Wei Chou
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Publication number: 20240321759Abstract: A package structure includes an interposer including a front side and a back side opposite the front side, an upper molded structure on the front side of the interposer and including an upper molding layer and a semiconductor die in the upper molding layer, and a lower molded structure on the back side of the interposer and including a lower molding layer and a substrate portion in the lower molding layer, wherein the substrate portion includes conductive layers electrically coupled to the semiconductor die through the interposer.Type: ApplicationFiled: June 30, 2023Publication date: September 26, 2024Inventors: Tsung-Ding Wang, Chien-Hsun Lee, Shang-Yun Hou, Hao-Cheng Hou, Chin-Liang Chen
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Publication number: 20240310733Abstract: A method includes forming a photoresist on a base structure, and performing a first light-exposure process on the photoresist using a first lithography mask. In the first light-exposure process, an inner portion of the photoresist is blocked from being exposed, and a peripheral portion of the photoresist is exposed. The peripheral portion encircles the inner portion. A second light-exposure process is performed on the photoresist using a second lithography mask. In the second light-exposure process, the inner portion of the photoresist is exposed, and the peripheral portion of the photoresist is blocked from being exposed. The photoresist is then developed.Type: ApplicationFiled: June 14, 2023Publication date: September 19, 2024Inventors: Shang-Yun Hou, Chien-Hsun Lee, Tsung-Ding Wang, Hao-Cheng Hou
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Publication number: 20240234302Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.Type: ApplicationFiled: March 26, 2024Publication date: July 11, 2024Inventors: Chung-Shi Liu, Chien-Hsun Lee, Jiun Yi Wu, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Li-Wei Chou
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PACKAGE STRUCTURE COMPRISING BUFFER LAYER FOR REDUCING THERMAL STRESS AND METHOD OF FORMING THE SAME
Publication number: 20240222215Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.Type: ApplicationFiled: March 14, 2024Publication date: July 4, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao -
Publication number: 20240128232Abstract: A semiconductor package includes a first semiconductor die, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The first semiconductor die includes a conductive post in a protective layer. The encapsulant encapsulates the first semiconductor die, wherein the encapsulant is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the protective layer, wherein the high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer, wherein the redistribution structure includes a redistribution dielectric layer, and the redistribution dielectric layer is made of a third material. The protective layer is made of a fourth material, and a ratio of a Young's modulus of the second material to a Young's modulus of the fourth material is at least 1.5.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Ding Wang, Yen-Fu Su, Hao-Cheng Hou, Jung-Wei Cheng, Chien-Hsun Lee, Hsin-Yu Pan
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Package structure comprising buffer layer for reducing thermal stress and method of forming the same
Patent number: 11961777Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.Type: GrantFiled: June 27, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao -
Publication number: 20240105631Abstract: Embodiments provide a method of performing a carrier switch for a device wafer, attaching a second wafer and removing a first wafer. A buffer layer is deposited over the device wafer, buffer layer reducing the topography of the surface of the device wafer. After the carrier switch a film-on-wire layer is removed from the buffer layer and then the buffer layer is at least in part removed.Type: ApplicationFiled: January 10, 2023Publication date: March 28, 2024Inventors: Jeng-An Wang, Sheng-Chi Lin, Hao-Cheng Hou, Tsung-Ding Wang, Chien-Hsun Lee
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Publication number: 20240071888Abstract: A package structure including a redistribution circuit structure, a wiring substrate, first conductive terminals, an insulating encapsulation, and a semiconductor device is provided. The redistribution circuit structure includes stacked dielectric layers, redistribution wirings and first conductive pads. The first conductive pads are disposed on a surface of an outermost dielectric layer among the stacked dielectric layers, the first conductive pads are electrically connected to outermost redistribution pads among the redistribution wirings by via openings of the outermost dielectric layer, and a first lateral dimension of the via openings is greater than a half of a second lateral dimension of the outermost redistribution pads. The wiring substrate includes second conductive pads. The first conductive terminals are disposed between the first conductive pads and the second conductive pads. The insulating encapsulation is disposed on the surface of the redistribution circuit structure.Type: ApplicationFiled: August 28, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chang Lin, Yen-Fu Su, Chin-Liang Chen, Wei-Yu Chen, Hsin-Yu Pan, Yu-Min Liang, Hao-Cheng Hou, Chi-Yang Yu
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Publication number: 20240071939Abstract: A semiconductor structure includes a composite redistribution structure, a first interconnect device and an integrated circuit (IC) package component. The composite redistribution structure includes a first redistribution structure, a second redistribution structure and a third redistribution structure. The second redistribution structure is located between the first redistribution structure and the third redistribution structure. The first interconnect device is embedded in the second redistribution structure. The first interconnect device includes a plurality of metal connectors leveled with a surface of the second redistribution structure and electrically connected to the third redistribution structure. The IC package component is disposed over the third redistribution structure and electrically connected to the first interconnect device via the third redistribution structure.Type: ApplicationFiled: August 28, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Hao-Cheng Hou
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Publication number: 20240071999Abstract: A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tseng Hsing Lin, Chien-Hsun Lee, Tsung-Ding Wang, Jung-Wei Cheng, Hao-Cheng Hou, Sheng-Chi Lin, Jeng-An Wang, Yao-Cheng Wu
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Publication number: 20240061037Abstract: A package structure includes a substrate component, a redistribution structure, a package structure, and a probe head. The substrate component is laterally covered by an insulating encapsulation. The redistribution structure is disposed over the substrate component and the insulating encapsulation and electrically connected with the substrate component at a first side, wherein the redistribution structure comprises: a dielectric layer at a second side opposite to the first side; at least one conductive pad disposed in the dielectric layer, wherein a portion of the at least one conductive pad is exposed by the dielectric layer; and at least one conductive pattern in contact with the portion of the at least one conductive pad, wherein a hardness of the at least one conductive pattern is greater than a hardness of the at least one conductive pad. The probe head is electrically connected with the at least one conductive pattern and the at least one conductive pad.Type: ApplicationFiled: August 17, 2022Publication date: February 22, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Cheng Hou, Jung-Wei Cheng, Tsung-Ding Wang, Chien-Hsun Lee
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Publication number: 20240055468Abstract: A method of forming an inductor including forming a first redistribution structure on a substrate, forming a first conductive via over and electrically connected to the first redistribution structure, depositing a first magnetic material over a top surface and sidewalls of the first conductive via, coupling a first die and a second die to the first redistribution structure, encapsulating the first die, the second die, and the first conductive via in an encapsulant, and planarizing the encapsulant and the first magnetic material to expose the top surface of the first conductive via while a remaining portion of the first magnetic material remains on sidewalls of the first conductive via, where the first conductive via and the remaining portion of the first magnetic material provide an inductor.Type: ApplicationFiled: January 23, 2023Publication date: February 15, 2024Inventors: Wei-Yu Chen, Chung-Hui Chen, Hao-Cheng Hou, Jung Wei Cheng, Tsung-Ding Wang, Chien-Hsun Lee, Shang-Yun Hou
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Publication number: 20240047322Abstract: A package structure and a manufacturing method thereof are provided. The package structure includes an integrated substrate and a package component. The integrated substrate includes a substrate component laterally covered by an insulating encapsulation, a redistribution structure disposed over the substrate component and the insulating encapsulation, first conductive joints coupling the redistribution structure to the substrate component, and a buffer layer disposed on a lowermost dielectric layer of the redistribution structure and extending downwardly to cover an upper portion of each of the first conductive joints. A lower portion of each of the first conductive joints connected to the upper portion is covered by the insulating encapsulation. The package component disposed over and electrically coupled to the redistribution structure includes a semiconductor die laterally covered by an encapsulant.Type: ApplicationFiled: August 4, 2022Publication date: February 8, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Liang Chen, Chi-Yang Yu, Yu-Min Liang, Hao-Cheng Hou, Jung-Wei Cheng, Tsung-Ding Wang
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Publication number: 20240047509Abstract: A method includes forming an inductor die, which includes forming a metal via over a substrate, forming a magnetic shell encircling the metal via, with the metal via and the magnetic shell collectively forming an inductor, and depositing a dielectric layer around the magnetic shell. The method further includes placing the inductor die over a carrier, encapsulating the inductor die in an encapsulant, forming redistribution lines electrically connecting to the inductor, and bonding a device die to the redistribution lines. The device die is electrically coupled to the inductor through the redistribution lines.Type: ApplicationFiled: January 5, 2023Publication date: February 8, 2024Inventors: Hao-Cheng Hou, Tsung-Ding Wang, Jung Wei Cheng, Chien-Hsun Lee, Shang-Yun Hou
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Patent number: 11894341Abstract: A semiconductor package includes a semiconductor die, an encapsulant, a first and second dielectric layer, a through via, an extension pad, and a routing via. The semiconductor die includes a contact post. The first dielectric layer extends on the encapsulant. The through via extends through the first dielectric layer and has one end contacting the contact post. The extension pad is disposed on the first dielectric layer, contacting an opposite end of the through via with respect to the contact post. The extension pad has an elongated shape, a first end of the extension pad overlaps with the contact post and the through via, and a second end of the extension pad overlaps with the encapsulant. The second dielectric layer is disposed on the first dielectric layer and the extension pad. The routing via extends through the second dielectric layer to contact the second end of the extension pad.Type: GrantFiled: February 2, 2021Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Ding Wang, Yen-Fu Su, Hao-Cheng Hou, Jung-Wei Cheng, Chien-Hsun Lee, Hsin-Yu Pan
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Publication number: 20240038646Abstract: Semiconductor device packages and methods of forming the same are discussed. In an embodiment, a device includes: a redistribution structure comprising an upper dielectric layer and an under-bump metallization; a buffer feature on the under-bump metallization and the upper dielectric layer, the buffer feature covering an edge of the under-bump metallization, the buffer feature bonded to the upper dielectric layer; a reflowable connector extending through the buffer feature, the reflowable connector coupled to the under-bump metallization; an interposer coupled to the reflowable connector; and an encapsulant around the interposer and the reflowable connector, the encapsulant different from the buffer feature.Type: ApplicationFiled: August 1, 2022Publication date: February 1, 2024Inventors: Chi-Yang Yu, Chin-Liang Chen, Hao-Cheng Hou, Jung Wei Cheng, Yu-Min Liang, Tsung-Ding Wang