Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, the metal gate structure being surrounded by an interlayer dielectric (ILD) layer; recessing the metal gate structure below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first dielectric layer over the recessed metal gate structure; forming an etch stop layer (ESL) over the first dielectric layer and the ILD layer; forming a second dielectric layer over the ESL; performing a first dry etch process to form an opening that extends through the second dielectric layer, through the ESL, and into the first dielectric layer; after the first dry etch process, performing a wet etch process to clean the opening; and after the wet etch process, performing a second dry etch process to extend the opening through the first dielectric layer.

Abstract: A method of making a Fin Field-effect transistor includes: providing a substrate and a plurality of fin structures on a surface of the substrate; forming a shallow trench isolation structure between the plurality of fin structures; forming a stress layer on a side of the shallow trench isolation structure away from the substrate; heat treating the stress layer and the plurality of fin structures; and removing the stress layer. The fin structures are spaced apart from each other. The stress layer covers a part of the fin structures away from the substrate.

Abstract: A semiconductor device structure and a formation method are provided. The method includes receiving a substrate, and the substrate has a dielectric layer and a semiconductor layer over the dielectric layer. The method also includes forming a p-type doped region and an n-type doped region in the semiconductor layer. The method further includes partially removing the semiconductor layer and the dielectric layer to form a recess exposing portions of the p-type doped region and the n-type doped region. In addition, the method includes forming a photo-sensing structure over sidewalls of the recess, and the photo-sensing structure is spaced apart from a bottom of the recess.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a p-type doped structure and an n-type doped structure. The method also includes forming a photo-sensing structure, and a portion of the photo-sensing structure is between the p-type doped structure and the n-type doped structure. The method further includes forming a semiconductor cap over the photo-sensing structure. The semiconductor cap is p-type doped.

Abstract: A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a P-type region and an N-type region. The P-type region and the N-type region are spaced apart from each other. The semiconductor device structure includes a light absorption structure in the substrate between the P-type region and an N-type region. The semiconductor device structure includes a first P-type film between the light absorption structure and the P-type region. The semiconductor device structure includes a second P-type film between the light absorption structure and the N-type region, wherein a portion of the substrate separates the second P-type film from the N-type region.

Abstract: The present disclosure provides constructs comprising a coding sequence operably linked to a promoter which expresses the polynucleotide in an outer hair cell, wherein the coding sequence encodes a polypeptide (e.g., a heterologous polypeptide). Exemplary constructs include AAV constructs. Also provided are methods of using disclosed constructs for the treatment of hearing loss and/or deafness.

Abstract: The present disclosure provides a bolometer including a substrate, a reflecting mirror on the substrate, and a temperature sensing unit above the reflecting mirror. The temperature sensing unit includes a first insulating layer, a thermistor on the first insulating layer, a second insulating layer on the thermistor, an electrode layer in the second insulating layer and right above the thermistor, and a metal meta-surface in the second insulating layer and right above the electrode layer. The electrode layer includes a plurality of electrodes separated from each other. A projection region of the metal meta-surface on the thermistor is equal to or larger than the thermistor.

Abstract: A display panel including a first substrate, a pixel-array layer, and a color-resist layer is disclosed. The pixel-array layer includes multiple first signal lines, multiple second signal lines, and multiple third signal lines. Each of the first signal lines corresponds to a common border between multiple first color resists and multiple second color resists. Each of the second signal lines corresponds to a common border between multiple third color resists and multiple first color resists. Each of the third signal lines corresponds to a common border between multiple second color resists and multiple third color resists. Reflected light coming from the first signal lines, reflected light coming from the second signal lines, and reflected light coming from the third signal lines are mixed to form white light.

Abstract: Various embodiments of the present disclosure are directed towards an optoelectronic device. The device includes a substrate, and a germanium photodiode region extending into an upper surface of the substrate. The germanium photodiode region has a curved upper surface that extends past the upper surface of the substrate. A silicon cap overlies the curved upper surface of the germanium photodiode region. There is an absence of oxide between the curved upper surface of the germanium photodiode region and an upper surface of the silicon cap.

Abstract: In some embodiments, the present disclosure relates to a semiconductor device, including a substrate including a first semiconductor material and a semiconductor layer extending into an upper surface of the substrate and including a second semiconductor material with a different band gap than the first semiconductor material. The semiconductor device also includes a passive cap including a first dielectric material and disposed along the upper surface of the substrate and on opposite sides of the semiconductor layer, and a photodetector in the semiconductor layer. The first dielectric material includes silicon nitride.

Abstract: Provided are a detection system, compensation method and computer-readable recording medium applicable to semiconductor surface morphology to provide feature information corresponding to spectral signals to a neural network model and provide feature information corresponding to spectral signals, a detected height, and an actual height actually measured to another neural network model. The combinational neural network models thus trained and built can generate a compensation value for a to-correct height corresponding to a to-correct spectral signal having variability. The compensation value provides required compensation for height information to not only enhance the precision of the detection of semiconductor surface morphology but also enhance the reliability of the detection system.

Abstract: A content-addressable memory includes a pre-search content-addressable memory array, a control circuit, and a main search content-addressable memory array. The pre-search content-addressable memory array is configured to perform a first data search to selectively adjust levels of a plurality of match lines in the pre-search content-addressable memory array. The control circuit is configured to generate a detection signal according to the levels of the plurality of match lines after the first data search is performed, and to generate an enable signal according to the detection signal. The main search content-addressable memory array is configured to selectively perform a second data search according to the enable signal.

Abstract: A semiconductor device includes: a photodiode including a germanium material portion laterally extending along a first horizontal direction, a p-doped silicon portion, and an n-doped silicon portion; and a distributed Bragg reflector including multiple periodic repetitions of a unit layer stack including a first material layer and a second material layer, wherein interfaces between vertically-extending portions of material layers within the distributed Bragg reflector are perpendicular to the first horizontal direction, and wherein the distributed Bragg reflector is in contact with the germanium material portion.

Abstract: A semiconductor die includes a plurality of first transistors and a second transistor. The first transistors are disposed in a peripheral area of the semiconductor die. Each of the first transistors has a first contact pad. In a top view, the first contact pad of each of the first transistors has a first outer edge in a hexagonal shape. The second transistor is disposed in a central area of the semiconductor die. The second transistor has a second contact pad. In the top view, the second contact pad has a second outer edge in a rectangular shape. The peripheral area surrounds the central area. The first contact pads of the first transistors collectively surround the second contact pad of the second transistor.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a doped region in the substrate. The semiconductor device further includes an active area, and wherein the active area comprises an emitter region and a collector region, wherein the emitter region is electrically connected to the doped region. The semiconductor device further includes a deep trench isolation (DTI) structure extending through the active area and between the emitter region and the collector region.

Abstract: A manufacturing method of a semiconductor structure includes the following operations. A stacked structure is formed on a substrate. The stacked structure includes semiconductor layers and sacrificial layers that are alternately stacked, in which the sacrificial layers include germanium, and germanium concentrations of the sacrificial layers decrease from bottom to top. A dummy gate structure is formed on the stacked structure. A spacer is formed on both sides of the dummy gate structure. The dummy gate structure is removed, thereby forming an opening. The sacrificial layers are removed from the opening. A gate structure is formed to cover the semiconductor layers. In another manufacturing method, the stacked structure includes semiconductor layers and sacrificial layers that are alternately stacked, in which thicknesses of the semiconductor layers increase from bottom to top, or thicknesses of the sacrificial layers increase from bottom to top.

Abstract: A masking circuit of a content addressable memory (CAM) includes a masking control circuit and a level control circuit. The masking control circuit generates a masking signal according to a word line (WL) signal and a write enablement (WE) signal. When both the WL and WE signals are at a first level, the masking signal is a first masking signal; when they are at different levels respectively, the masking signal is a second masking signal. The level control circuit generates a level control signal according to the masking signal for determining whether to pull a voltage level of a match line of the CAM to a predetermined level. When the masking signal is the first masking signal, the level control circuit pulls the voltage level to the predetermined level; and when the masking signal is the second masking signal, the level control circuit does not interfere in the voltage level.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a doped well in the substrate, wherein the doped well comprises a first concentration of dopants of a first type in the substrate. The semiconductor device further includes a doped region in the substrate, wherein the doped region comprises a second concentration of the dopants of the first type, the doped region extends around the doped well, and the doped region is electrically insulated from the doped well. The semiconductor device further includes an active area, and wherein the active area comprises an emitter region and a collector region, wherein the emitter region is electrically connected to the doped region. The semiconductor device further includes a deep trench isolation (DTI) structure extending through the active area and between the emitter region and the collector region.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a sensor semiconductor layer. The sensor semiconductor layer is doped with a first dopant. A photodetector is along a frontside of the sensor semiconductor layer. A backside semiconductor layer is along a backside of the sensor semiconductor layer, opposite the frontside. The backside semiconductor layer is doped with a second dopant. A diffusion barrier structure is between the sensor semiconductor layer and the backside semiconductor layer. The diffusion barrier structure includes a third dopant different from the first dopant and the second dopant.