Patents by Inventor Hao-Chieh Yung

Hao-Chieh Yung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6660593
    Abstract: A method for fabricating oxide layers with different thicknesses on a substrate is described. A field oxide layer is formed on the substrate to define a first active region and a second active region therebetween. A first oxide layer is formed over the first active region. A thin oxynitride layer is formed on the first oxide layer.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: December 9, 2003
    Assignee: Winbond Electronics Corp.
    Inventors: Shing-Sing Chiang, Kuo-Shi Teng, Hao-Chieh Yung, Yi-Shi Chen
  • Publication number: 20020081798
    Abstract: A method for fabricating oxide layers with different thicknesses on a substrate is described. A field oxide layer is formed on the substrate to define a first active region and a second active region therebetween. A first oxide layer is formed over the first active region. A thin oxynitride layer is formed on the first oxide layer.
    Type: Application
    Filed: December 21, 2000
    Publication date: June 27, 2002
    Inventors: Shing-Sing Chiang, Kuo-Shi Teng, Hao-Chieh Yung, Yi-Shi Chen
  • Patent number: 6307266
    Abstract: A metal-line structure in an integrated circuit (IC) and a method of fabricating the same are provided. The metal-line structure includes a barrier layer formed at a selected location over the dielectric layer, a metallization layer formed over the barrier layer, an ARC formed over the metallization layer, and a spacer structure formed over all the exposed sidewalls of the barrier layer, the metallization layer, and the ARC. The forming of the spacer structure on each of the metal lines can help prevent the occurrence of extrusions along the sidewalls of the metal lines in the IC device that would otherwise cause dielectric cracks and thus lead to undesired bridging between neighboring metal lines as in the prior art. Moreover, the method of fabricating such a metal-line structure can be carried out without having to perform photolithography, thus reducing manufacturing cost.
    Type: Grant
    Filed: July 20, 2000
    Date of Patent: October 23, 2001
    Assignee: Winbond Electronics Corp.
    Inventor: Hao-Chieh Yung
  • Patent number: 6127252
    Abstract: A metal-line structure in an integrated circuit (IC) and a method of fabricating the same are provided. The metal-line structure includes a barrier layer formed at a selected location over the dielectric layer, a metallization layer formed over the barrier layer, an ARC formed over the metallization layer, and a spacer structure formed over all the exposed sidewalls of the barrier layer, the metallization layer, and the ARC. The forming of the spacer structure on each of the metal lines can help prevent the occurrence of extrusions along the sidewalls of the metal lines in the IC device that would otherwise cause dielectric cracks and thus lead to undesired bridging between neighboring metal lines as in the prior art. Moreover, the method of fabricating such a metal-line structure can be carried out without having to perform photolithography, thus reducing manufacturing cost.
    Type: Grant
    Filed: October 1, 1998
    Date of Patent: October 3, 2000
    Assignee: Winbond Electronics Corp.
    Inventor: Hao-Chieh Yung
  • Patent number: 6075280
    Abstract: This invention discloses a novel method for separating a semiconductor wafer into a plurality of integrated circuit (IC) chips. The separation is carried out along scribe lines between the IC chips. The method includes steps of (a) forming a photoresist layer on the semiconductor wafer; (b) performing a photolithography process for removing the photoresist layer above the scribe lines between the IC chips; (c) performing an etch process for removing a dielectric layer above the scribe lines between the IC chips for exposing the scribe lines on the semiconductor wafer; (d) performing a wet chemical etch process to anisotropically etch the semiconductor wafer into a V-shaped groove in the scribe lines; and (e) applying a mechanical force to break the semi-conductor wafer along the V-shaped grooves in the scribe lines thus separating the semiconductor wafer into a plurality of IC chips.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: June 13, 2000
    Assignee: Winbond Electronics Corporation
    Inventors: Hao-Chieh Yung, Gene Jing-Chiang Chang
  • Patent number: 6034439
    Abstract: A method for preventing bonding pads from peeling caused by plug process comprises the following steps. First, a substrate is prepared, and then a first conductor is formed on the substrate. Next, a dielectric layer is formed on the first conductor. After that, a big contact window and a plurality of small contact windows are formed on the dielectric layer, wherein the plurality of small contact windows are located around the big window, and the sizes of the big contact window and small contact windows are over 3 .mu.m. Subsequently, a metal plug layer is formed on the dielectric layer, big contact window and small contact windows. Thereafter, the metal plug layer is etched back to form metal spacers on the sidewalls of the big contact window and small contact windows. Finally, a second conductor is formed on the dielectric layer, big contact window, small contact windows and metal spacers.
    Type: Grant
    Filed: March 12, 1998
    Date of Patent: March 7, 2000
    Assignee: Winbond Electronics Corporation
    Inventors: Kuo-Shi Teng, Hao-Chieh Yung, Shing-Shing Chiang, Wen-Haw Lu