Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a base structure. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching the channel structures. The semiconductor device structure further includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. In addition, the semiconductor device structure includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.

Abstract: An electronic device includes a substrate, a driving element, a first insulating layer, a pixel electrode layer, and a common electrode layer. The driving element is disposed on the substrate. The first insulating layer is disposed on the driving element. The pixel electrode layer is disposed on the first insulating layer. The first insulating layer comprises a hole, and the pixel electrode layer is electrically connected to the driving element through the hole. The common electrode layer is disposed on the pixel electrode layer. The common electrode layer comprises a slit, and the slit has an edge, and the edge is disposed in the hole.

Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.

Abstract: A light-emitting touch panel includes a circuit board, a plurality of light-emitting elements, a shading plate and a cover plate. The light emitting element has a first height in a first direction. The shading plate has a plurality of spacing regions corresponding to the light emitting elements, respectively. A first width is provided between two partition walls of each spacing region in a second direction. Each partition wall has a second height in the first direction, and the second height is greater than the first height. The cover plate has a light-transmitting region, the light emitted by the light-emitting elements passes through the light-transmitting region, and a bright region is formed on the top surface of the cover plate away from the shading plate, wherein a second width of the bright region in the second direction is related to the second height and the first width.

Abstract: A staining kit is provided, including a first pattern including antibodies against T cell, B cell, NK cell, monocyte, regulatory cell, CD8, CD45, and CTLA4; a second pattern including antibodies against T cell, B cell, NK cell, monocyte, regulatory cell, dendritic cell, and CD45; a third pattern including antibodies against T cell, B cell, NK cell, monocyte, CD8, CD45, CD45RA, CD62L, CD197, CX3CR1 and TCR??; and a fourth pattern including antibodies against B cell, CD23, CD38, CD40, CD45 and IgM, wherein the antibodies of each pattern are labeled with fluorescent dyes. A method of identifying characterized immune cell subsets of a disease and a method of predicting the likelihood of NPC in a subject in the need thereof using the staining kit are also provided.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.

Abstract: A video decoding method includes: before residual decoding of a coding unit is completed, referring to available information to determine whether to decode information that an inverse transform (IT) circuit needs for applying inverse transform to transform blocks of the coding unit, and generating a determination result; and controlling coefficient transmission of the coding unit to the IT circuit according to the determination result.

Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).

Abstract: The present invention relates to a pitch-variable battery fixture and a battery cell formation apparatus having the same. A pitch of clamping plates of a plurality of clamping blocks is increased by a slide actuator of the pitch-variable battery fixture, and then the clamping plates are inserted into a plurality of compartments of a battery tray. The clamping plates are urged to clamp batteries by the slide actuator. The battery tray is provided for placement of the batteries, and a compressing force is exerted for shaping the batteries during a battery cell formation. The pitch-variable battery fixture is provided for clamping batteries having different thicknesses. According to the actual thickness of each battery, the thickness of the formed battery can be shaped.

Abstract: A device includes: a stack of semiconductor nanostructures; a gate structure wrapping around the semiconductor nanostructures, the gate structure extending in a first direction; a source/drain region abutting the gate structure and the stack in a second direction transverse the first direction; a contact structure on the source/drain region; a backside conductive trace under the stack, the backside conductive trace extending in the second direction; a first through via that extends vertically from the contact structure to a top surface of the backside dielectric layer; and a gate isolation structure that abuts the first through via in the second direction.

Abstract: A contact stack of a semiconductor device includes a source/drain feature, a silicide layer wrapping around the source/drain feature, a seed metal layer in direct contact with the silicide layer, and a conductor in contact with the seed metal layer. The contact stack excludes a metal nitride layer in direct contact with the silicide layer.

Abstract: A backlight module and an electronic device are provided. The backlight module, having a main region and a peripheral region near the main region, includes a light conversion layer, multiple light conversion patterns located in the peripheral region, and multiple light emitting units emitting a light beam. A first portion and a second portion of the light beam emitted respectively from the main region and the peripheral region both have at least one corresponding position in a CIE 1931 color space. One among the at least one corresponding position of the first portion of the light beam has corresponding coordinates (x1, y1). One among the at least one corresponding position of the second portion of the light beam has corresponding coordinates (x2, y2). The corresponding coordinates (x1, y1) and the corresponding coordinates (x2, y2) satisfy the following relation: 0?|x1?x2|?0.2.

Abstract: The present invention relates to the use of compounds of formula (I) and formula (II) and/or pharmaceutically acceptable salts of the aforementioned compounds in the treatment of meningioma and the reduction of the recurrence rate of meningioma. In formulas (I) and (II), R1 is C1-C20 alkyl, C3-C10 cycloalkyl, C6-C20 aryl, C1-C20 alkoxy, C6-C20 aryloxy, or halogen; p is 0 to 3; R2 is H, C1-C20 alkyl, or C6-C20 aryl; and R3 is H, C1-C20 alkyl, C3-C10 cycloalkyl, or C6-C20 aryl.

Abstract: A battery pack for an information handling system includes a battery cell configured to provide current to the information handling system, and a battery management unit including an output to the information handling system. The output provides a maximum continuous current (MCC) indication and a peak power (PP) indication. The battery management unit determines an amount of current that the battery cell provides to the information handling system and determines an optimum MCC value that the battery cell can provide to the information handling system. The battery management unit further provides a first value on the PP indication, the first value being greater than the optimum MCC value, sums the amount of current provided to the information handling system that is in excess of the optimum MCC value, determines that the sum is greater than a threshold, and provides a second value on the PP indication, the second value being less than the optimum MCC value.

Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.

Abstract: A semiconductor image sensor includes a pixel. The pixel includes a first substrate; and a photodiode in the first substrate. The semiconductor image sensor further includes an interconnect structure electrically connected to the pixel. The semiconductor image sensor further includes a reflection structure between the interconnect and the photodiode, wherein the reflection structure is configured to reflect light passing through the photodiode back toward the photodiode.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.