Abstract: A system for controlling a vehicle, including one or more communication modules and one or more processors operably coupled to the communication modules. The one or more processors are configured to individually or collectively: receive a geo-fence identifier associated with geo-fence information, where the geo-fence identifier uniquely identifies the geo-fence from other geo-fences; obtain one or more activity regulations for the vehicle based on the geo-fence identifier; and control operation of the vehicle according to the one or more activity regulations.

Abstract: A portable lighting device includes a housing, a light source supported by the housing, and an alkaline battery positioned within the housing and coupled to the light source. The alkaline battery is configured to provide a drive current to the light source, and an intensity of the light source is dependent on the drive current. The portable lighting device also includes an electronic processor positioned within the housing and coupled to the light source and the alkaline battery. The electronic processor is configured to monitor a voltage of the alkaline battery, and execute a ramp-up algorithm to control the drive current based on the voltage of the alkaline battery.

Abstract: Systems and methods are provided for calculating, using an electronic processor, an average environmental brightness and determining a current pulse width modulation (“PWM”) output level provided to the light source. The method also includes determining, using the electronic processor, a target illumination level and a PWM adjustment rate. The PWM adjustment rate is based at least partially on the calculated average environmental brightness. The method also includes adjusting, using the electronic processor, the current PWM output level at the determined PWM adjustment rate to reach the target illumination level, and transmitting the adjusted PWM output level to the light source. The target illumination level is determined as a function of the current PWM output level and an output mode of the light source.

Abstract: A semiconductor device includes a peripheral circuit pattern on a substrate including first and second regions, a bit line structure on the peripheral circuit pattern electrically connected to the peripheral circuit pattern on the first region of the substrate, a channel on and electrically connected to the bit line structure, a word line at a side of the channel, a capacitor on and electrically connected to the channel, a plate electrode on an upper surface and a sidewall of the capacitor, an etch stop pattern on the second region of the substrate, and a first through via on and electrically connected to the peripheral circuit pattern on the second region of the substrate. A lower surface of the etch stop pattern is coplanar with a lower surface of the channel, and the first through via extends through the etch stop pattern in a vertical direction, and contacts the plate electrode.

Abstract: A semiconductor device includes a bit line structure, a back gate electrode and a word line on the bit line structure, an active pattern between the back gate electrode and the word line, on the bit line structure, the active pattern extending in a vertical direction, a back gate dielectric layer between the back gate electrode and the active pattern, the back gate dielectric layer on a side surface and a lower surface of the back gate electrode, and a first insulating structure between the back gate dielectric layer and the bit line structure. The first insulating structure includes a first stopper in contact with the back gate dielectric layer and the bit line structure. The back gate dielectric layer is spaced apart from the bit line structure by the first stopper in the vertical direction.

Abstract: A vertical, fin-based field effect transistor (FinFET) device includes an array of individual FinFET cells. The array includes a plurality of rows and columns of separated fins. Each of the separated fins is in electrical communication with a source contact. The vertical FinFET device also includes one or more rows of first inactive fins disposed on a first set of sides of the array of individual FinFET cells, one or more columns of second inactive fins disposed on a second set of sides of the array of individual FinFET cells, and a gate region surrounding the individual FinFET cells of the array of individual FinFET cells, the first inactive fins, and the second inactive fins.

Abstract: A III-N-based vertical transistor includes a III-N substrate, a source, a drain, and a channel comprising a III-N crystal material and extending between the source and the drain. The channel includes at least one sidewall surface aligned ±0.3° with respect to an m-plane of the III-N crystal material. The III-N-based vertical transistor also includes a gate electrically coupled to the at least one sidewall surface of the channel.

Abstract: A vertical, fin-based field effect transistor (FinFET) device includes an array of individual FinFET cells. The array includes a plurality of rows and columns of separated fins. Each of the separated fins is in electrical communication with a source contact. The vertical FinFET device also includes one or more rows of first inactive fins disposed on a first set of sides of the array of individual FinFET cells, one or more columns of second inactive fins disposed on a second set of sides of the array of individual FinFET cells, and a gate region surrounding the individual FinFET cells of the array of individual FinFET cells, the first inactive fins, and the second inactive fins.

Abstract: A III-N-based vertical transistor includes a III-N substrate, a source, a drain, and a channel comprising a III-N crystal material and extending between the source and the drain. The channel includes at least one sidewall surface aligned ±0.3° with respect to an m-plane of the III-N crystal material. The III-N-based vertical transistor also includes a gate electrically coupled to the at least one sidewall surface of the channel.

Abstract: A semiconductor device includes an active device region and a plurality of guard rings arranged in a first concentric pattern surrounding the active device region. The semiconductor device also includes a plurality of junctions arranged in a second concentric pattern surrounding the active device region. At least one of the plurality of junctions is arranged between two adjacent guard rings of the plurality of guard rings, and the plurality of junctions have a different resistivity than the plurality of guard rings. The semiconductor device further includes a plurality of coupling paths. At least one of the plurality of coupling paths is arranged to connect two adjacent guard rings of the plurality of guard rings.

Abstract: An aerial vehicle includes a communication unit configured to receive a wireless signal from a geo-fencing device, and a flight controller configured to generate one or more control signals that cause the aerial vehicle to operate in accordance with a set of flight regulations generated based on the wireless signal. The geo-fencing device is configured not for landing of the aerial vehicle. The set of flight regulations includes rules for controlling at least one of the aerial vehicle, a carrier carried by the aerial vehicle, or a payload of the aerial vehicle.

Abstract: A method for preparing a self-supporting composite nanofiltration membrane is provided. A porous graphene-based two-dimensional sheet material is prepared by taking amino graphene quantum dots as the main body and subjecting them to an interfacial polymerization reaction with polyacyl chloride, and then the porous graphene-based two-dimensional sheet material is encapsulated in-situ with polyamide by an in-situ encapsulating technology to prepare a self-supporting porous graphene/polyamide separation layer with excellent permeability and high selectivity.

Abstract: A vertical MOSFET includes a substrate and a first III-nitride layer of a first conductivity type and having a first dopant concentration coupled to the substrate. First trenches are within the first III-nitride layer. A second III-nitride structure of a second dopant concentration and a second conductivity type opposite to the first conductivity type are within the first trenches. A third III-nitride layer of the second conductivity type is coupled to the first III-nitride layer and the second III-nitride structure. A fourth III-nitride layer of the first conductivity type coupled to the third III-nitride layer. Second trenches are within the third and fourth III-nitride layers. A gate dielectric and a gate conductor are within the second trenches. A source conductor is coupled to an upper portion of the fourth III-nitride layer. The first III-nitride layer and the second III-nitride structure provide a charge balance structure.

Abstract: A semiconductor device includes an active device region and a plurality of guard rings arranged in a first concentric pattern surrounding the active device region. The semiconductor device also includes a plurality of junctions arranged in a second concentric pattern surrounding the active device region. At least one of the plurality of junctions is arranged between two adjacent guard rings of the plurality of guard rings, and the plurality of junctions have a different resistivity than the plurality of guard rings. The semiconductor device further includes a plurality of coupling paths. At least one of the plurality of coupling paths is arranged to connect two adjacent guard rings of the plurality of guard rings.

Abstract: A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.

Abstract: A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.

Abstract: An unmanned aerial vehicle (UAV) includes a sensor configured to detect an indicator of a geo-fencing device; and a flight controller configured to generate one or more signals that cause the UAV to operate in accordance with a set of flight regulations that are generated based on the detected indicator of the geo-fencing device.

Abstract: A system for controlling a vehicle, including one or more communication modules and one or more processors operably coupled to the communication modules. The one or more processors are configured to individually or collectively: receive a geo-fence identifier associated with geo-fence information, where the geo-fence identifier uniquely identifies the geo-fence from other geo-fences; obtain one or more activity regulations for the vehicle based on the geo-fence identifier; and control operation of the vehicle according to the one or more activity regulations.

Abstract: A method for manufacturing a vertical FET device includes providing a semiconductor substrate structure including a semiconductor substrate and a first semiconductor layer coupled to the semiconductor substrate. The first semiconductor layer is characterized by a first conductivity type. The method also includes forming a plurality of semiconductor fins coupled to the first semiconductor layer. Each of the plurality of semiconductor fins is separated by one of a plurality of recess regions. The method further includes epitaxially regrowing a semiconductor gate layer including a surface region in the plurality of recess regions. The method also includes forming an isolation region within the surface region of the semiconductor gate layer. The isolation region surrounds each of the plurality of semiconductor fins. The method includes forming a source contact structure coupled to each of the plurality of semiconductor fins and forming a gate contact structure coupled to the semiconductor gate layer.

Abstract: A method for manufacturing a vertical FET device includes providing a semiconductor substrate structure including a semiconductor substrate and a first semiconductor layer coupled to the semiconductor substrate. The first semiconductor layer is characterized by a first conductivity type. The method also includes forming a plurality of semiconductor fins coupled to the first semiconductor layer. Each of the plurality of semiconductor fins is separated by one of a plurality of recess regions. The method further includes epitaxially regrowing a semiconductor gate layer including a surface region in the plurality of recess regions. The method also includes forming an isolation region within the surface region of the semiconductor gate layer. The isolation region surrounds each of the plurality of semiconductor fins. The method includes forming a source contact structure coupled to each of the plurality of semiconductor fins and forming a gate contact structure coupled to the semiconductor gate layer.