Patents by Inventor Hao-Hsiang Chuang

Hao-Hsiang Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220320024
    Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 11398440
    Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Publication number: 20190057946
    Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 10109605
    Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 10090243
    Abstract: An inductor includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of contacts. Each of the first conductive lines is spaced apart from one another. Each of the second conductive lines is spaced apart from one another, and each of the second conductive lines crosses over each of the first conductive lines. Each of the contacts electrically interconnects one of the first conductive lines and one of the second conductive lines. These contacts are arranged in a way such that at least parts of the first conductive lines and at least parts of the second conductive lines form an electric current path serving as an inductor.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: October 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hao-Hsiang Chuang, Jeng-Shien Hsieh, Chuei-Tang Wang, Chen-Hua Yu
  • Publication number: 20160254224
    Abstract: An inductor includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of contacts. Each of the first conductive lines is spaced apart from one another. Each of the second conductive lines is spaced apart from one another, and each of the second conductive lines crosses over each of the first conductive lines. Each of the contacts electrically interconnects one of the first conductive lines and one of the second conductive lines. These contacts are arranged in a way such that at least parts of the first conductive lines and at least parts of the second conductive lines form an electric current path serving as an inductor.
    Type: Application
    Filed: May 10, 2016
    Publication date: September 1, 2016
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hao-Hsiang CHUANG, Jeng-Shien HSIEH, Chuei-Tang WANG, Chen-Hua YU
  • Patent number: 9355956
    Abstract: An inductor includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of contacts. Each of the first conductive lines is spaced apart from one another. Each of the second conductive lines is spaced apart from one another, and each of the second conductive lines crosses over each of the first conductive lines. Each of the contacts electrically interconnects one of the first conductive lines and one of the second conductive lines. These contacts are arranged in a way such that at least parts of the first conductive lines and at least parts of the second conductive lines form an electric current path serving as an inductor.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: May 31, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hao-Hsiang Chuang, Jeng-Shien Hsieh, Chuei-Tang Wang, Chen-Hua Yu
  • Publication number: 20150311169
    Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.
    Type: Application
    Filed: June 17, 2015
    Publication date: October 29, 2015
    Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 9082761
    Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.
    Type: Grant
    Filed: June 1, 2013
    Date of Patent: July 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Publication number: 20150123759
    Abstract: An inductor includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of contacts. Each of the first conductive lines is spaced apart from one another. Each of the second conductive lines is spaced apart from one another, and each of the second conductive lines crosses over each of the first conductive lines. Each of the contacts electrically interconnects one of the first conductive lines and one of the second conductive lines. These contacts are arranged in a way such that at least parts of the first conductive lines and at least parts of the second conductive lines form an electric current path serving as an inductor.
    Type: Application
    Filed: November 1, 2013
    Publication date: May 7, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., LTD.
    Inventors: Hao-Hsiang Chuang, Jeng-Shien Hsieh, Chuei-Tang Wang, Chen-Hua Yu
  • Publication number: 20140353819
    Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.
    Type: Application
    Filed: June 1, 2013
    Publication date: December 4, 2014
    Inventors: Hao-Hsiang Chuang, Shih-Wei Liang, Ching-Feng Yang, Kai-Chiang Wu, Hao-Yi Tsai, Chuei-Tang Wang, Chen-Hua Yu
  • Patent number: 8542075
    Abstract: A method for reducing EM radiation comprises at least one first resonance line disposed on one of electric surfaces, which is disposed at a side of a transmission line structure on one of the electric surface. The resonance line crosses over a slot of another electric surface. The slot is etched on a corresponding electric surface. In addition, the transmission line structure crosses over the slot of the electric surface. Then, the first resonance line connects the electric surface having the slot with another electric surface. It can adjust at least one of a length, a width and a shape of the first resonance line, to make an input impedance seen from a crossed point between the transmission line structure and the slot approximately 0.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: September 24, 2013
    Assignee: National Taiwan University
    Inventors: Tzong-Lin Wu, Hao-Hsiang Chuang
  • Patent number: 8508311
    Abstract: A transmission line with a structure which is capable of forming a passive equalizer and an electrical apparatus using the same are illustrated. The transmission line has a substrate, a ground plane, a defect ground structure, a pair of transmission conducting lines, and at least one stub. The substrate has a plurality of surfaces. The ground plane is located on at least one of the surfaces. The defect ground structure is formed on the ground plane. The pair of transmission conducting lines is located on one of the surfaces, and stretching over the defect ground structure. The at least one stub is located above a plane of the defect ground structure, extending along with at least one side of two sides of the pair of the transmission conducting lines, and electrically coupled to the pair of the transmission conducting lines and the ground plane.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: August 13, 2013
    Assignee: National Taiwan University
    Inventors: Tzong-Lin Wu, Hao-Hsiang Chuang, Yu-Ren Cheng
  • Publication number: 20130038413
    Abstract: A transmission line with a structure which is capable of forming a passive equalizer and an electrical apparatus using the same are illustrated. The transmission line has a substrate, a ground plane, a defect ground structure, a pair of transmission conducting lines, and at least one stub. The substrate has a plurality of surfaces. The ground plane is located on at least one of the surfaces. The defect ground structure is formed on the ground plane. The pair of transmission conducting lines is located on one of the surfaces, and stretching over the defect ground structure. The at least one stub is located above a plane of the defect ground structure, extending along with at least one side of two sides of the pair of the transmission conducting lines, and electrically coupled to the pair of the transmission conducting lines and the ground plane.
    Type: Application
    Filed: October 13, 2011
    Publication date: February 14, 2013
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: TZONG-LIN WU, HAO-HSIANG CHUANG, YU-REN CHENG
  • Publication number: 20120188025
    Abstract: A method for reducing EM radiation comprises at least one first resonance line disposed on one of electric surfaces, which is disposed at a side of a transmission line structure on one of the electric surface. The resonance line crosses over a slot of another electric surface. The slot is etched on a corresponding electric surface. In addition, the transmission line structure crosses over the slot of the electric surface. Then, the first resonance line connects the electric surface having the slot with another electric surface. It can adjust at least one of a length, a width and a shape of the first resonance line, to make an input impedance seen from a crossed point between the transmission line structure and the slot approximately 0.
    Type: Application
    Filed: March 23, 2011
    Publication date: July 26, 2012
    Applicant: National Taiwan University
    Inventors: Tzong-Lin WU, Hao-Hsiang Chuang