Patents by Inventor Hao-Hsiang Yang

Hao-Hsiang Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145919
    Abstract: An antenna module includes a first metal plate and a frame body. The frame body surrounds the first metal plate. The frame body includes a first antenna radiator, a second antenna radiator, a third antenna radiator, a first breakpoint and a second breakpoint. The first antenna radiator includes a first feeding end and excites a first frequency band. The second antenna radiator includes a second feeding end and excites a second frequency band. The third antenna radiator includes a third feeding end and excites a third frequency band. The first breakpoint is located between the first antenna radiator and the second antenna radiator. The second breakpoint is located between the second antenna radiator and the third antenna radiator. An electronic device including the above-mentioned antenna module is also provided.
    Type: Application
    Filed: September 6, 2023
    Publication date: May 2, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Shih-Keng Huang, Chao-Hsu Wu, Chih-Wei Liao, Sheng-Chin Hsu, Hao-Hsiang Yang, Tse-Hsuan Wang
  • Publication number: 20240113429
    Abstract: An electronic device including a bracket and an antenna is provided. The bracket includes first, second, third, and fourth surfaces. The antenna includes a radiator. The radiator includes first, second, third, and fourth portions. The first portion is located on the first surface and includes connected first and second sections. The second portion is located on the second surface and includes third, fourth, fifth, and sixth sections. The third section, the fourth section, and the fifth sections are bent and connected to form a U shape. The third portion is located on the third surface and is connected to the second section and the fourth section. The fourth portion is located on the fourth surface and is connected to the fifth section, the sixth section, and the third portion. The radiator is adapted to resonate at a low frequency band and a first high frequency band.
    Type: Application
    Filed: August 16, 2023
    Publication date: April 4, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Sheng-Chin Hsu, Chia-Hung Chen, Chih-Wei Liao, Hau Yuen Tan, Hao-Hsiang Yang, Shih-Keng Huang
  • Patent number: 11871507
    Abstract: An electronic device includes a casing, a circuit board and at least one antenna module. The casing has an accommodating space and an inner side wall surrounding the accommodating space. The circuit board is disposed in the accommodating space. Each of the antenna modules includes a first radiator and a second radiator. The first radiator is disposed on the circuit board and adjacent to the inner side wall, and includes a first section, a second section and a third section extending from the first section in opposite directions respectively. The first section includes a feeding end, and the third section includes a grounding end. The second radiator is disposed on the inner side wall. A coupling gap is formed between the first radiator and the second radiator.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: January 9, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Cheng-Jui Huang, Hao-Hsiang Yang, Shih-Keng Huang
  • Publication number: 20240006769
    Abstract: An electronic device including a metal bottom plate, a metal frame and at least one radiator is provided. The metal bottom plate includes at least one ground terminal. The metal frame includes at least one slot, at least one disconnecting part, at least one first connecting part and at least one second connecting part. The disconnecting part includes a first part and a second part. Each radiator includes a first terminal and a second terminal. The second terminal is connected to a junction between the first part and the second part. The first terminal, the second terminal, the first part, the first connecting part and the ground terminal form a first antenna path radiating at a first frequency band. The first terminal, the second terminal, the second part, the second connecting part and the ground terminal form a second antenna path radiating at a second frequency band.
    Type: Application
    Filed: May 15, 2023
    Publication date: January 4, 2024
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chih-Wei Liao, Chao-Hsu Wu, Hau Yuen Tan, Shih-Keng Huang, Cheng-Hsiung Wu, Chia-Hung Chen, Sheng-Chin Hsu, Hao-Hsiang Yang
  • Publication number: 20230155296
    Abstract: An antenna module includes two antenna units, two isolation members, and a grounding member. Each antenna unit consists of two feeding ends. two first radiators, and two second. radiators. The isolating members are disposed between the first and second portions of each antenna unit. The grounding member is disposed beside the two antenna units and the two isolation members. A first slot is formed among each first radiator, the second radiator, and the grounding member. The two second radiators are connected to the third radiator. A third slot is formed between the second radiator and the second portion. The two antenna units are symmetric to the fourth slot in a mirrored manner, and the two first portions have widths gradually changing along an extending direction of the fourth position.
    Type: Application
    Filed: October 13, 2022
    Publication date: May 18, 2023
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Cheng-Hsiung Wu, Chia-Hung Chen, Shih-Keng Huang, Hau Yuen Tan, Sheng-Chin Hsu, Tse-Hsuan Wang, Hao-Hsiang Yang
  • Publication number: 20230033219
    Abstract: An electronic device, including a metal back cover, a front cover, a metal wall, and at least one antenna radiator, is provided. The front cover covers the metal back cover and includes a frame area. The metal wall is disposed between the metal back cover and the front cover, and forms a metal cavity corresponding to the frame area together with the metal back cover. Each of the at least one antenna radiator is disposed in the metal cavity, is connected to a first side wall of the metal back cover, and is spaced apart from the metal wall by a distance.
    Type: Application
    Filed: May 17, 2022
    Publication date: February 2, 2023
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Hau Yuen Tan, Chao-Hsu Wu, Cheng-Hsiung Wu, Chen-Kuang Wang, Shih-Keng Huang, Chia-Hung Chen, Sheng-Chin Hsu, Hao-Hsiang Yang
  • Publication number: 20220167494
    Abstract: An electronic device includes a casing, a circuit board and at least one antenna module. The casing has an accommodating space and an inner side wall surrounding the accommodating space. The circuit board is disposed in the accommodating space. Each of the antenna modules includes a first radiator and a second radiator. The first radiator is disposed on the circuit board and adjacent to the inner side wall, and includes a first section, a second section and a third section extending from the first section in opposite directions respectively. The first section includes a feeding end, and the third section includes a grounding end. The second radiator is disposed on the inner side wall. A coupling gap is formed between the first radiator and the second radiator.
    Type: Application
    Filed: September 23, 2021
    Publication date: May 26, 2022
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Chao-Hsu Wu, Cheng-Jui Huang, Hao-Hsiang Yang, Shih-Keng Huang
  • Patent number: 11247340
    Abstract: This disclosure is related to a non-contact tool center point calibration method for a robot arm, and the method comprises: obtaining a coordinate transformation relationship between a flange surface of the robot arm and cameras by a hand-eye calibration algorithm; constructing a space coordinate system by a stereoscopic reconstruction method; actuating a replaceable member fixed with the flange surface to present postures in a union field of view of the cameras sequentially, recording feature coordinates of the replaceable member in the space coordinate system, and recording flange surface coordinates which is under the postures in the space coordinate system; obtaining a transformation relationship between a tool center point and the flange surface; and updating the transformation relationship into a control program of the robot arm. Moreover, the disclosure further discloses a calibration device performing the calibration method and a robot arm system having the calibration function.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: February 15, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng Chieh Hsu, Hao Hsiang Yang, Shu Huang, Yan Yi Du
  • Publication number: 20200198145
    Abstract: This disclosure is related to a non-contact tool center point calibration method for a robot arm, and the method comprises: obtaining a coordinate transformation relationship between a flange surface of the robot arm and cameras by a hand-eye calibration algorithm; constructing a space coordinate system by a stereoscopic reconstruction method; actuating a replaceable member fixed with the flange surface to present postures in a union field of view of the cameras sequentially, recording feature coordinates of the replaceable member in the space coordinate system, and recording flange surface coordinates which is under the postures in the space coordinate system; obtaining a transformation relationship between a tool center point and the flange surface; and updating the transformation relationship into a control program of the robot arm. Moreover, the disclosure further discloses a calibration device performing the calibration method and a robot arm system having the calibration function.
    Type: Application
    Filed: December 26, 2018
    Publication date: June 25, 2020
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng Chieh HSU, Hao Hsiang YANG, Shu HUANG, Yan Yi DU
  • Patent number: 10629734
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
  • Publication number: 20190172949
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Application
    Filed: January 18, 2019
    Publication date: June 6, 2019
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
  • Patent number: 10229995
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: March 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
  • Publication number: 20190027602
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Application
    Filed: August 4, 2017
    Publication date: January 24, 2019
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
  • Publication number: 20180358453
    Abstract: The present invention provides a method of making a tunneling effect transistor (TFET), the method includes: a substrate is provided, having a fin structure disposed thereon, the fin structure includes a first conductive type, a dielectric layer is then formed on the substrate and on the fin structure, a gate trench is formed in the dielectric layer, and a first work function metal layer is formed in the gate trench, the first work function metal layer defines at least a left portion, a right portion and a central portion, an etching process is performed to remove the central portion of the first work function metal layer, and to form a recess between the left portion and the right portion of the first work function metal layer, afterwards, a second work function metal layer is formed and filled in the recess.
    Type: Application
    Filed: July 6, 2017
    Publication date: December 13, 2018
    Inventors: Hung-Wen Huang, Kai-Lin Lee, Ren-Yu He, Chi-Hsiao Chen, Ting-Hsuan Kang, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh