Patents by Inventor Hao-Hua Hsu

Hao-Hua Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250015073
    Abstract: A semiconductor device that includes an n-buried layer, a p-well region over the n-buried layer, an n-channel MOSFET that includes an n-drain region, and a vertical NPN BJT having a collector that is the n-drain region and a base that is the p-well region. The p-well region is floating.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 9, 2025
    Inventors: Ken-Hao FAN, Yu-Ti Su, Sheng-Fu Hsu, Hao-Hua Hsu
  • Publication number: 20240371858
    Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Hsiao-Ching Huang, Sheng-Fu Hsu, Hao-Hua Hsu, Pin-Chen Chen, Lin-Yu Huang, Yu-Chang Jong
  • Patent number: 12132042
    Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: October 29, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Ching Huang, Sheng-Fu Hsu, Hao-Hua Hsu, Pin-Chen Chen, Lin-Yu Huang, Yu-Chang Jong
  • Publication number: 20240030215
    Abstract: The ability of a grounded gate NMOS (ggNMOS) device to withstand and protect against human body model (HBM) electrostatic discharge (ESD) events is greatly increased by resistance balancing straps. The resistance balancing straps are areas of high resistance formed in the substrate between an active area that includes a MOSFET of the ggNMOS device and a bulk ring that surrounds the active area. A Vss rail is coupled to the substrate beneath the MOSFET through the bulk ring. The substrate beneath the MOSFET provides base regions for parasitic transistors that switch on for the ggNMOS device to operate. The straps inhibit low resistance pathways between the base regions and the bulk ring and prevent a large portion of the ggNMOS device from being switched off while a remaining portion of the ggNMOS device remains switched on. The strap may be divided into segments inserted at strategic locations.
    Type: Application
    Filed: July 25, 2022
    Publication date: January 25, 2024
    Inventors: Hsiao-Ching Huang, Sheng-Fu Hsu, Hao-Hua Hsu, Pin-Chen Chen, Lin-Yu Huang, Yu-Chang Jong
  • Publication number: 20230395592
    Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first semiconductor device and second semiconductor device disposed on a semiconductor substrate. The first semiconductor device comprises a first gate structure, a first source region, and a first drain region. The first source and drain regions and are disposed in a first well region. The second semiconductor device comprises a second gate structure, a second source region, and a second drain region. The second source and drain regions are disposed in a second well region. The first and second well regions comprise a first doping type. The first well region is laterally offset from the second well region by a first distance. A third well region is disposed in the semiconductor substrate and laterally between the first and second well regions. The third well region comprises a second doping type opposite the first doping type.
    Type: Application
    Filed: June 3, 2022
    Publication date: December 7, 2023
    Inventors: Hsiao-Ching Huang, Hao-Hua Hsu, Sheng-Fu Hsu