Abstract: A signal receiver includes a data receiver and a data strobe signal receiver. The data receiver includes a plurality of current mode logic circuits and a plurality of data latches. A first stage current mode logic circuit receives a data signal, and a final stage current mode logic circuit outputs an amplified data signal. The plurality of data latches receive the amplified data signal, wherein each of the data latches sums the amplified data signal and a plurality of feedback data to obtain a summing data, and latches the summing data to output an output data according to one of a plurality of amplified data strobe signals. The data strobe signal receiver receives a data strobe signal, and generates the plurality of amplified data strobe signals by dividing a frequency of the data strobe signal.

Abstract: A memory device and a control method of the memory device are provided. The memory device includes a memory array and a control logic circuit. The memory array includes a plurality of memory cell rows. The control logic circuit perform an access on the memory array. The control logic circuit counts a number of the access performed on the memory cell rows to generate a plurality of count values corresponding to the memory cell rows. When a count value corresponding to an accessed memory cell row among the memory cell rows is larger than or equal to a threshold value generated with random number corresponding to the accessed memory cell row, the control logic circuit arranges the memory cell rows nearby the accessed memory cell row into a mitigation operation.

Abstract: A low dropout regulator is disclosed. The low dropout regulator includes an amplifier, a transistor, and a selector. The transistor is coupled to the amplifier. The selector is coupled to the amplifier and the transistor. When a supply voltage value of the transistor is less than a supply voltage threshold value, a first path of the selector is selected and a first selector voltage value is transmitted by the selector to the transistor so as to fully conduct the transistor, and an output voltage value of the transistor is equal to the supply voltage value.

Abstract: A low dropout regulator is disclosed. The low dropout regulator includes an amplifier, a first transistor, a second transistor and a switch. When a supply voltage value of the low dropout regulator is less than a supply voltage threshold value, a first path of the switch is selected and a first switch voltage value is transmitted to the first transistor so as to fully conduct the first transistor, and an output voltage value of the low dropout regulator is equal to the supply voltage value. When the supply voltage value is not less than the supply voltage threshold value, a second path of the switch is selected and a second switch voltage value is transmitted to the first transistor so as to turn off the first transistor, and the output voltage value is adjusted by the second transistor and the amplifier.

Abstract: A low dropout regulator is disclosed. The low dropout regulator includes an amplifier, a first transistor, a second transistor and a switch. When a supply voltage value of the low dropout regulator is less than a supply voltage threshold value, a first path of the switch is selected and a first switch voltage value is transmitted to the first transistor so as to fully conduct the first transistor, and an output voltage value of the low dropout regulator is equal to the supply voltage value. When the supply voltage value is not less than the supply voltage threshold value, a second path of the switch is selected and a second switch voltage value is transmitted to the first transistor so as to turn off the first transistor, and the output voltage value is adjusted by the second transistor and the amplifier.

Abstract: A low dropout regulator is disclosed. The low dropout regulator includes an amplifier, a transistor, and a selector. The transistor is coupled to the amplifier. The selector is coupled to the amplifier and the transistor. When a supply voltage value of the transistor is less than a supply voltage threshold value, a first path of the selector is selected and a first selector voltage value is transmitted by the selector to the transistor so as to fully conduct the transistor, and an output voltage value of the transistor is equal to the supply voltage value.

Abstract: An off chip driving circuit includes a decision circuit, a first compensation circuit, a second compensation circuit, a pull-up circuit and a pull-down circuit. The decision circuit is configured to output a first decision signal and a second decision signal according to a clock and an input data. The first compensation circuit is coupled to the decision circuit and configured to generate a first control signal in response to the first decision signal and the second decision signal. The second compensation circuit is coupled to the decision circuit and configured to generate a second control signal in response to the first decision signal and the second decision signal. The pull-up circuit is configured to be enabled in response to the first control signal. The pull-down circuit is configured to be enabled in response to the second control signal.

Abstract: A system includes a first circuit, a second circuit and a regulator. The first circuit is configured to operate at a first operating voltage, wherein the first operating voltage drops by a first voltage level while the first circuit operates. The second circuit is coupled with the first circuit at a tap, and configured to operate at a second operating voltage. The regulator is configured to provide a supply voltage to the first circuit and the second circuit via the tap. The regulator is also configured to raise the supply voltage in response to the first voltage level.

Abstract: A system includes a first circuit, a second circuit and a regulator. The first circuit is configured to operate at a first operating voltage, wherein the first operating voltage drops by a first degree while the first circuit operates. The second circuit is coupled with the first circuit at a tap, and configured to operate at a second operating voltage. The regulator is configured to provide a supply voltage to the first circuit and the second circuit via the tap. The regulator is also configured to raise the supply voltage in response to the first degree.

Abstract: A system includes a regulator, a first circuit and a first sensing circuit. The regulator is configured to provide a supply voltage, and to raise the supply voltage based on a sensing result. The first circuit is configured to operate at a first operating voltage, which is derived from the supply voltage. The first sensing circuit, independent of the regulator, is configured to provide a first sensing result by sensing the first operating voltage provided to the first circuit, wherein the first sensing result serves as a first candidate for the sensing result, wherein the first sensing circuit in space of layout is closer than the regulator to the first circuit.

Abstract: A system includes a regulator, a first circuit and a first sensing circuit. The regulator is configured to provide a supply voltage, and to raise the supply voltage based on a sensing result. The first circuit is configured to operate at a first operating voltage, which is derived from the supply voltage. The first sensing circuit, independent of the regulator, is configured to provide a first sensing result by sensing the first operating voltage provided to the first circuit, wherein the first sensing result serves as a first candidate for the sensing result, wherein the first sensing circuit in space of layout is closer than the regulator to the first circuit.

Abstract: The invention relates to a method for reducing the PAPR in FRFT-OFDM systems, which belongs to the field of broadband wireless digital communications technology. The method is based on fractional random phase sequence and fractional circular convolution theorem, which can effectively reduce the PAPR of the system. The method of the invention has the advantages of simple system implementation and low computational complexity. In this method, the PAPR of the system can be effectively reduced while maintaining the reliability of the system. When the number of candidate signals is the same, the PAPR performance of the present method was found to be almost the same as that of SLM and better than that of PTS. More importantly, the present method has lower computational complexity than that of SLM and PTS methods.

Abstract: The invention relates to a method for reducing the PAPR in FRFT-OFDM systems, which belongs to the field of broadband wireless digital communications technology. The method is based on fractional random phase sequence and fractional circular convolution theorem, which can effectively reduce the PAPR of the system. The method of the invention has the advantages of simple system implementation and low computational complexity. In this method, the PAPR of the system can be effectively reduced while maintaining the reliability of the system. When the number of candidate signals is the same, the PAPR performance of the present method was found to be almost the same as that of SLM and better than that of PTS. More importantly, the present method has lower computational complexity than that of SLM and PTS methods.

Abstract: The invention relates to a method that low complexity suppression of PAPR in FRFT-OFDM system, which belongs to the field of broadband wireless digital communications technology and can be used to reduce the PAPR in FRFT-OFDM system. The method is based on fractional random phase sequence and fractional circular convolution theorem, which can effectively reduce the PAPR of system. The method of the invention has the advantages of simple system implementation and low computational complexity. In this method, the PAPR of the system can be effectively reduced while keeping the system reliability. When the number of candidate signals is the same, the PAPR performance of the proposed method was found to be almost the same as that of SLM and better than that of PTS. More importantly, the proposed method has lower computational complexity than that of SLM and PTS.

Abstract: A digital audio/video playback system capable of controlling audio and video playback speed for decoding a digital audio/video signal and then outputting such signal. The system includes: a loader configured to receive the digital audio/video signals, a parser configured to resolve the digital audio/video signals into a video bitstream and an audio bitstream, a video decoder and an audio decoder respectively configured to receive and decode the video bitstream and the audio bitstream, and a playback speed controller configured to adjust the sound frequency of the decoded audio based on a set playback speed and output the decoded video/audio at the set playback speed.

Abstract: A digital audio/video playback system capable of controlling audio and video playback speed for decoding a digital audio/video signal and then outputting such signal. The system includes: a loader configured to receive the digital audio/video signals, a parser configured to resolve the digital audio/video signals into a video bitstream and an audio bitstream, a video decoder and an audio decoder respectively configured to receive and decode the video bitstream and the audio bitstream, and a playback speed controller configured to adjust the sound frequency of the decoded audio based on a set playback speed and output the decoded video/audio at the set playback speed.