Patents by Inventor Hao-Jen Liao

Hao-Jen Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reduction of OCD measurement noise by way of metal via slots
    Patent number: 9252060
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches.
    Type: Grant
    Filed: April 1, 2012
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Tsai, Liang-Guang Chen, Han-Hsin Kuo, Fu-Ming Huang, Hao-Jen Liao, Ming-Chung Liang
  • REDUCTION OF OCD MEASUREMENT NOISE BY WAY OF METAL VIA SLOTS
    Publication number: 20130256659
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches.
    Type: Application
    Filed: April 1, 2012
    Publication date: October 3, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chi-Ming Tsai, Liang-Guang Chen, Han-Hsin Kuo, Fu-Ming Huang, Hao-Jen Liao, Ming-Chung Liang