Abstract: A bath massage chair includes a pillow, a back support configured to support a torso of the user when the user is seated in the bath massage chair, and a seat coupled to the lower portion of the back support. The pillow includes a pillow massage system and a pillow heating element configured to heat the pillow. The back support includes an upper portion coupled to the pillow and a lower portion opposite the upper portion, a back massage system configured to massage the torso of the user, and a back heating element configured to heat the back support. The seat is configured to support a lower body of the user when the user is seated in the bath massage chair. The pillow massage system, pillow heating element, back massage system, and back heating element are operably coupled to a controller.

Abstract: A circuit includes a supply voltage node having a supply voltage value and a node having a node voltage, the node voltage having a node voltage value higher than the supply voltage value. A current generating circuit is coupled between the supply voltage node and the node and is configured to generate a current, and a tracking circuit electrically coupled to the node is configured to selectively supply the current to the node based on the node voltage.

Abstract: A circuit includes a supply voltage node having a supply voltage value and a node having a node voltage, the node voltage having a node voltage value higher than the supply voltage value. A current generating circuit is coupled between the supply voltage node and the node and is configured to generate a current, and a tracking circuit electrically coupled to the node is configured to selectively supply the current to the node based on the node voltage.

Abstract: A circuit includes a switching circuit, a node, and a tracking circuit. The switching circuit has a first terminal, a second terminal, and a third terminal. The node has a node voltage. The tracking circuit is electrically coupled to the third terminal and the node, and configured to receive the node voltage and generate a control voltage at the third terminal based on the node voltage.

Abstract: A voltage swing decomposition circuit includes first and second clamp circuits and a protection circuit. The first clamp circuit is configured to clamp an output node of the first clamp circuit at a first voltage level when an input node of the voltage swing decomposition circuit has a voltage higher than the first voltage level. The second clamp circuit is configured to clamp an output node of the second clamp circuit at a second voltage level, higher than the first level, when the voltage of the input node is lower than the second voltage level. The protection circuit is coupled to the output nodes of the first and second clamp circuits, and is configured to selectively set an output node of the protection circuit to the first or second voltage level. The first and second clamp circuits are coupled together by the output node of the protection circuit.

Abstract: A squelch detector includes a first circuit, a second circuit, and a comparator. The first circuit is configured to receive a first pair of differential input signals and in response output a second pair of differential signals. The second pair of differential signals have higher voltages than the first pair of differential input signals. The second circuit is coupled to the first circuit and is configured to extract first and second voltage levels from the second pair of differential signals. The comparator is configured to output a squelch level signal based on a comparison of the first voltage level and a third voltage level. The third voltage level is based on the second voltage level and a reference voltage.

Abstract: A D flip-flop includes a first switch, a level shifter, and a second switch therein. The first switch includes a first input and a first output. The level shifter includes a second input coupled to the first input, and a second output. The second switch includes a third input coupled to the second output, and a third output. The first input and the third output form an input and an output of the D flip-flop.

Abstract: A D flip-flop includes a first switch, a level shifter, and a second switch therein. The first switch includes a first input and a first output. The level shifter includes a second input coupled to the first input, and a second output. The second switch includes a third input coupled to the second output, and a third output. The first input and the third output form an input and an output of the D flip-flop.

Abstract: A voltage swing decomposition circuit includes first and second clamp circuits and a protection circuit. The first clamp circuit is configured to clamp an output node of the first clamp circuit at a first voltage level when an input node of the voltage swing decomposition circuit has a voltage higher than the first voltage level. The second clamp circuit is configured to clamp an output node of the second clamp circuit at a second voltage level, higher than the first level, when the voltage of the input node is lower than the second voltage level. The protection circuit is coupled to the output nodes of the first and second clamp circuits, and is configured to selectively set an output node of the protection circuit to the first or second voltage level. The first and second clamp circuits are coupled together by the output node of the protection circuit.

Abstract: An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other.

Abstract: A circuit includes a switching circuit, a node, and a tracking circuit. The switching circuit has a first terminal, a second terminal, and a third terminal. The node has a node voltage. The tracking circuit is electrically coupled to the third terminal and the node, and configured to receive the node voltage and generate a control voltage at the third terminal based on the node voltage.

Abstract: A squelch detector includes a first circuit, a second circuit, and a comparator. The first circuit is configured to receive a first pair of differential input signals and in response output a second pair of differential signals. The second pair of differential signals have higher voltages than the first pair of differential input signals. The second circuit is coupled to the first circuit and is configured to extract first and second voltage levels from the second pair of differential signals. The comparator is configured to output a squelch level signal based on a comparison of the first voltage level and a third voltage level. The third voltage level is based on the second voltage level and a reference voltage.

Abstract: An integrated circuit (IC), comprises a receiver on an IC substrate. The receiver is configured to receive a stressed input signal. A built in self test (BIST) circuit is provided on the IC substrate for testing the receiver. The BIST circuit comprises an encoder configured for receiving an input signal and identifying whether a first condition is present, in which two or more consecutive input data bits have the same polarity as each other. An output driver circuit provides the stressed input signal corresponding to the two or more consecutive input data bits. The stressed input signal has an amplitude that is larger when the encoder identifies that the first condition is present and smaller when the encoder identifies that two or more consecutive input data bits have different polarity from each other.

Abstract: The present invention provides a method and apparatus for detecting speech spectral peaks and a speech recognition method and system. The method for detecting speech spectral peaks comprises detecting speech spectral peak candidates from power spectrum of the speech, and removing noise peaks from the speech spectral peak candidates according to peak duration and/or peak positions of adjacent frames, to detect speech spectral peaks. In the present invention, reliable speech spectral peaks can be obtained by removing noise peaks using the limitations of peak duration and adjacent frames in the detection of the speech spectral peaks. Further the energy values of the speech spectral peaks are used to extract the MFCC feature of speech instead of a sample sequence of the whole power spectrum in the conventional technique, the noise robustness of speech recognition can be enhanced while not increasing the speech feature dimensions.

Abstract: A method for verification of speaker authentication comprises inputting a test utterance containing a password that is spoken by a speaker, extracting an acoustic feature vector sequence from the inputted test utterance, obtaining a matching path between the extracted acoustic feature vector sequence and a speaker template enrolled by an enrolled speaker, calculating a matching score of the obtained matching path upon considering spectral change of the test utterance and/or spectral change of the speaker template, and comparing the matching score with a predefined discriminating threshold to determine whether the inputted test utterance is an utterance containing a password spoken by the enrolled speaker.

Abstract: A method includes, generating, for each parameter of the prosody vector, an initial parameter prediction model with a plurality of attributes related to difference prosody prediction and at least part of attribute combinations of the plurality of attributes, in which each of the plurality of attributes and the attribute combinations is included as an item, calculating importance of each item in the parameter prediction model, deleting the item having the lowest importance calculated, re-generating a parameter prediction model with the remaining items, determining whether the re-generated parameter prediction model is an optimal model, and repeating the step of calculating importance and the steps following the step of calculating importance with the re-generated parameter prediction model, if the re-generated parameter prediction model is determined as not an optimal model, wherein the difference prosody vector and all parameter prediction models of the difference prosody vector constitute the difference pros