Abstract: An array substrate includes a pixel unit, a data line, a first gate line and a second gate line. Adjacent two columns of pixel units are collectively connected to one data line, adjacent two of the pixel units in each row of pixel units are respectively connected to the first and second gate lines, the pixel unit includes a transistor, and the transistor in each pixel unit is provided adjacent to the data line. In adjacent two columns of pixel units, transistors of two diagonally adjacent pixel units are provided adjacent to the data line and connected respectively to the first and second gate lines. The first and second gate lines surround the gate electrode of the transistor, respectively, and the first and second gate lines are connected to the gate electrode of the transistor at positions of the gate electrode away from the data line.

Abstract: An array substrate includes a pixel unit, a data line, a first gate line and a second gate line. Adjacent two columns of pixel units are collectively connected to one data line, adjacent two of the pixel units in each row of pixel units are respectively connected to the first and second gate lines, the pixel unit includes a transistor, and the transistor in each pixel unit is provided adjacent to the data line. In adjacent two columns of pixel units, transistors of two diagonally adjacent pixel units are provided adjacent to the data line and connected respectively to the first and second gate lines. The first and second gate lines surround the gate electrode of the transistor, respectively, and the first and second gate lines are connected to the gate electrode of the transistor at positions of the gate electrode away from the data line.