Patents by Inventor Hao Liao

Hao Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12387457
    Abstract: An image capturing device with a sensor, a memory, and a processor is provided. The sensor captures an image of at least one target. The memory stores a plurality of instructions. The processor obtains the plurality of instructions to perform the following steps: controlling the sensor to capture a reference image and a processed image; capturing a first bright region and a dark region from the reference image, and capturing a second bright region from the processed image; performing calculations on a first brightness value of the first bright region and a second brightness value of the second bright region respectively with at least two first brightness thresholds, to obtain a first low exposure compensation value and a second low exposure compensation value; and obtaining a high exposure compensation value according to comparisons between a third brightness value of the dark region and at least two second brightness thresholds.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: August 12, 2025
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chun-Hao Liao, Hsiu-Ting Yang
  • Publication number: 20250246491
    Abstract: A package includes a die, an encapsulant, and a redistribution structure. The encapsulant laterally encapsulates the die. The redistribution structure includes a first portion directly above the encapsulant and a second portion directly above the die. A thickness of the first portion of the redistribution structure decreases continuously from an edge of the package toward an interior of the package.
    Type: Application
    Filed: April 22, 2025
    Publication date: July 31, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 12374629
    Abstract: An electromagnetic interference (EMI) shielding package structure, a manufacturing method thereof, and an electronic assembly are provided. The EMI shielding package structure includes a carrier, at least one chip mounted on a first board surface of the carrier, an encapsulant formed on the carrier and packaging the at least one chip, an EMI shielding layer formed on an outer surface of the encapsulant, and an insulating layer. The insulating layer includes a spraying portion and a capillary permeating portion. The spraying portion is formed at least part of an outer surface of the EMI shielding layer. The capillary permeating portion is formed by extending from a bottom end of the spraying portion toward a second board surface of the carrier through capillarity, and the capillary permeating portion covers a bottom edge of the EMI shielding layer.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: July 29, 2025
    Assignee: AZUREWAVE TECHNOLOGIES, INC.
    Inventors: Chih-Hao Liao, Shu-Han Wu, Hsin-Yeh Huang
  • Patent number: 12368046
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.
    Type: Grant
    Filed: December 18, 2023
    Date of Patent: July 22, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee
  • Publication number: 20250230851
    Abstract: An apparatus is provided. The apparatus includes an equipment support structure configured to support a semiconductor fabrication component. The apparatus includes a damper assembly configured to resist a lateral force induced by a seismic event to the equipment support structure. The damper assembly includes a gear rack coupled to the equipment support structure. The damper assembly includes a first flywheel assembly including a first mass damper flywheel and a first gear meshed with the gear rack and selectively engaged with the first mass damper flywheel.
    Type: Application
    Filed: January 12, 2024
    Publication date: July 17, 2025
    Inventors: Chen Hao LIAO, Chih-Tsung LEE, Ming-Yi LIN, Cheng-Lung WU, Jiun-Rong PAI
  • Patent number: 12354881
    Abstract: A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.
    Type: Grant
    Filed: February 26, 2024
    Date of Patent: July 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai, Chung-Ju Lee
  • Publication number: 20250215064
    Abstract: A novel fusion protein to overcome the current difficulties related to application of monoclonal antibodies in disease treatment and in other fields, particularly those requiring ADCC, e.g. for depletion of tumor cells, virally-infected cells, or immune-modulating cells, etc. One example of the fusion protein is an extracellular domain of a high-affinity variant of human CD 16 A fused to an anti-CD3 antibody or its antigen-binding fragment thereof that specifically binds to an epitope on human CD3 or a fragment thereof.
    Type: Application
    Filed: January 18, 2025
    Publication date: July 3, 2025
    Applicant: MANYSMART THERAPEUTICS, INC.
    Inventors: HSIN-YI HUANG, CHENG HAO LIAO, CHUN-MING LIN
  • Patent number: 12334433
    Abstract: A semiconductor device including a semiconductor die, an encapsulant and a redistribution structure is provided. The encapsulant laterally encapsulates the semiconductor die. The redistribution structure is disposed on the semiconductor die and the encapsulant and is electrically connected to the semiconductor die. The redistribution structure includes a dielectric layer, a conductive via in the dielectric layer and a redistribution wiring covering the conductive via and a portion of the dielectric layer. The conductive via includes a pillar portion embedded in the dielectric layer and a protruding portion protruding from the pillar portion, wherein the protruding portion has a tapered sidewall.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sih-Hao Liao, Hung-Jui Kuo, Yu-Hsiang Hu
  • Publication number: 20250189889
    Abstract: A method of manufacturing a semiconductor device includes applying a polymer mixture over a substrate, exposing and developing at least a portion of the polymer mixture to form a developed dielectric, and curing the developed dielectric to form a dielectric layer. The polymer mixture includes a polymer precursor, a photosensitizer, and a solvent. The polymer precursor may be a polyamic acid ester.
    Type: Application
    Filed: February 14, 2025
    Publication date: June 12, 2025
    Inventors: Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
  • Publication number: 20250191971
    Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.
    Type: Application
    Filed: February 19, 2025
    Publication date: June 12, 2025
    Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Shau-Lin Shue, Yu-Teng Dai, Wei-Hao Liao
  • Publication number: 20250191973
    Abstract: In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.
    Type: Application
    Filed: February 18, 2025
    Publication date: June 12, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee
  • Patent number: 12322688
    Abstract: A package structure includes a first redistribution layer, a semiconductor die and a second redistribution layer. The first redistribution layer includes a first dielectric layer, first conductive elements, second conductive elements, a top dielectric layer and an auxiliary dielectric portion. The first conductive elements and the second conductive elements are disposed on the first dielectric layer with a first pattern density and a second pattern density respectively. The top dielectric layer is disposed on the first dielectric layer and covering a top surface of the second conductive elements. The auxiliary dielectric portion is disposed in between the first dielectric layer and the top dielectric layer, and covering a top surface of the first conductive elements. The semiconductor die is disposed on the first redistribution layer. The second redistribution layer is disposed on the semiconductor die, and electrically connected to the semiconductor die and the first redistribution layer.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Han Wang, Sih-Hao Liao, Wei-Chih Chen, Hung-Chun Cho, Ting-Chen Tseng, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 12322723
    Abstract: The present disclosure relates to a semiconductor structure including an interconnect structure disposed over a semiconductor substrate. A lower metal line is disposed at a first height over the semiconductor substrate and extends through a first interlayer dielectric layer. A second interlayer dielectric layer is disposed at a second height over the semiconductor substrate and comprises a first dielectric material. An upper metal line is disposed at a third height over the semiconductor substrate. A via is disposed at the second height. The via extends between the lower metal line and the upper metal line. A protective dielectric structure is disposed at the second height. The protective dielectric structure comprises a protective dielectric material and is disposed along a first set of opposing sidewalls of the via, the protective dielectric material differing from the first dielectric material.
    Type: Grant
    Filed: July 26, 2023
    Date of Patent: June 3, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao
  • Patent number: 12315772
    Abstract: A package includes a die, an encapsulant, and a redistribution structure. The encapsulant laterally encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure partially exposes the die. A top surface of the redistribution structure is slanted downward continuously from an edge of the package toward an interior of the package.
    Type: Grant
    Filed: July 19, 2023
    Date of Patent: May 27, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 12315817
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a dielectric on wire structure is arranged directly over the interconnect wire. Outer sidewalls of the dielectric on wire structure are surrounded by the first interconnect dielectric layer. The integrated chip further includes a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect via that extends through the second interconnect dielectric layer and the dielectric on wire structure to contact the interconnect wire.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: May 27, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai, Wei-Hao Liao
  • Patent number: 12302761
    Abstract: A device includes a first dielectric layer, a magnetic tunnel junction (MTJ), an oxide layer, a cap layer, and a second dielectric layer. The MTJ is over the first dielectric layer. The oxide layer is over the first dielectric layer. The cap layer is over the first dielectric layer. The cap layer is in contact with a sidewall of the MTJ and a sidewall of the oxide layer. The second dielectric layer is over the cap layer.
    Type: Grant
    Filed: September 25, 2023
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih-Wei Lu, Chung-Ju Lee
  • Patent number: 12298667
    Abstract: A method includes the following steps. A photoresist is exposed to a first light-exposure through a first mask, wherein the first mask includes a first stitching region, and a first portion of the photoresist corresponding to a first opaque portion of the first stitching region is unexposed. The photoresist is exposed to a second light-exposure through a second mask, wherein the second mask includes a second stitching region, and a second portion of the photoresist corresponding to a second opaque portion of the second stitching region is unexposed and is overlapping with the first portion of the photoresist.
    Type: Grant
    Filed: December 28, 2023
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Che Tu, Po-Han Wang, Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 12300611
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate, a second interconnect dielectric layer arranged over the first interconnect dielectric layer, and an interconnect conductive structure arranged within the second interconnect dielectric layer. The interconnect conductive structure includes an outer portion that includes a first conductive material. Further, the interconnect conductive structure includes a central portion having outermost sidewalls surrounding by the outer portion of the interconnect conductive structure. The central portion includes a second conductive material different than the first conductive material.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: May 13, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Teng Dai, Hsi-Wen Tien, Wei-Hao Liao, Hsin-Chieh Yao, Chih Wei Lu, Chung-Ju Lee
  • Patent number: 12293988
    Abstract: A semiconductor package includes a semiconductor die and a redistribution structure. The semiconductor die is laterally surrounded by a molding compound, and the semiconductor die has a conductive pillar and a complex compound sheath sandwiched between the conductive pillar and the molding compound. The redistribution structure is electrically connected with the semiconductor die and comprises a first via portion at a first side of the redistribution structure and a second via portion at a second side of the redistribution structure, and a base angle of the second via portion is greater than a base angle of the first via portion.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Hung-Chun Cho
  • Publication number: 20250139978
    Abstract: A vehicle violation detection method and vehicle violation detection system are provided. The method includes the following steps. A video clip including a plurality of consecutive frames is obtained, wherein the video clip is generated through photographing an intersection by an image capture device. A traffic sign object corresponding to a traffic sign and a license plate object corresponding to a license plate are detected from each of the frames. According to a sign position of the traffic sign object and a plate position of the license plate object in each of the frames, vehicle behavior information of each of the frames is obtained. By conducting regression analysis to the vehicle behavior information of each of the frames, whether a vehicle violation event has occurred is determined.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 1, 2025
    Applicant: National Chengchi University
    Inventors: Yan-Tsung Peng, Chen-Yu Liu, He-Hao Liao, Wei-Cheng Lien