Patents by Inventor Hao-Lin Chiu
Hao-Lin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170084214Abstract: A display may have an array of pixels arranged in rows and columns. Display driver circuitry may be provided along an edge of the display. Data lines that are associated with columns of the pixels may be used to distribute data from the display driver circuitry to the pixels. Gate lines in the display may each have a horizontal straight portion that extends along a respective row of the pixels and may each have one or more non-horizontal segments such as zigzag segments. The non-horizontal portion of each gate line may be connected to the horizontal straight portion of the gate line by a via. The non-horizontal portions may each have portions that are overlapped by portions of the data lines. Dummy gate line structures may be provided on the display that are not coupled to any of the pixels in the display.Type: ApplicationFiled: May 24, 2016Publication date: March 23, 2017Inventors: Shinya Ono, Chun-Yao Huang, Hao-Lin Chiu, Ivan Knez, Patrick B. Bennett, Shih Chang Chang, Byung Duk Yang
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Publication number: 20170084247Abstract: A display device may include pixels and source lines that provide data line signals to the pixels. The display device may also include gate lines that provide gate signals to switches associated with the pixels. The display device may also include vertical gate lines disposed generally parallel to the source lines and coupled to the gate lines at cross point nodes. The display device may also include compensation lines, such that each compensation line is proximate to a respective vertical gate line. The compensation lines may transmit compensation signals having an opposite polarity as compared to respective gate signals to reduce or eliminate a kickback voltage on at least one of the plurality of pixels.Type: ApplicationFiled: September 21, 2015Publication date: March 23, 2017Inventors: Byung Duk Yang, Chun-Yao Huang, Kyung Wook Kim, Patrick B. Bennett, Shih Chang Chang, Wonjae Choi, Hao-Lin Chiu, Kwang Soon Park, Xinyu Zhu
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Publication number: 20170061837Abstract: A display device may include a plurality of pixels, a plurality of source lines that may provide a plurality of data line signals to the plurality of pixels, a plurality of gate lines that may provide a plurality of gate signals to a plurality of switches associated with the plurality of pixels, and a plurality of voltage gate lines disposed parallel to the plurality of source lines and coupled to the plurality of gate lines at a plurality of cross point nodes. The plurality of cross point nodes are positioned in a pseudo random order across the display device.Type: ApplicationFiled: January 14, 2016Publication date: March 2, 2017Inventors: Howard H. Tang, Wei Chen, Paolo Sacchetto, Chaohao Wang, Chun-Yao Huang, Hao-Lin Chiu
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Publication number: 20160334658Abstract: A display has an array of pixels controlled by display driver circuitry. Gate driver circuitry supplies gate line signals to rows of the pixels. The pixels may be liquid crystal display pixels. Each pixel may have a common electrode voltage terminal. The display may have a transparent conductive film that forms a common electrode voltage layer that overlaps that array and that is shorted to the common electrode voltage terminals of the pixels. Metal common electrode voltage lines may run across the transparent conductive film to reduce resistance. Metal common electrode voltage paths that are coupled to the metal common electrode voltage lines may run along the left and right edge of the display. Common electrode voltage compensation circuits may receive feedback from the metal common electrode voltage paths. There may be two or more common electrode voltage compensation circuits for both the left and right edges of the display.Type: ApplicationFiled: May 14, 2015Publication date: November 17, 2016Inventors: Young-Jik Jo, Chun-Yao Huang, Hao-Lin Chiu, Kwang Soon Park, Shih Chang Chang
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Publication number: 20160321975Abstract: A display may have a first stage such as a color liquid crystal display stage and a second stage such as a monochromatic liquid crystal display stage that are coupled in tandem so that light from a backlight passes through both stages. The pixel pitch of the second stage may be greater than the pixel pitch of the first stage to ease alignment tolerances and reduce image processing complexity. The first stage may be provided with straight black masking strips, whereas the second stage may be provided with angled zigzagging black masking strips. The angle of the zigzagging black masking strips and the ratio of the pixel pitch of the second stage to that of the first stage may be selected to maximize optical transmittance while minimizing Moire effects.Type: ApplicationFiled: September 23, 2015Publication date: November 3, 2016Inventors: Jin Yan, Young Cheol Yang, Jun Jiang, Hao-Lin Chiu, Young-Jik Jo, Cheng Chen
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Publication number: 20160098144Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.Type: ApplicationFiled: October 26, 2015Publication date: April 7, 2016Inventors: Byung Duk Yang, Szu-Hsien Lee, Kyung Wook Kim, Shih Chang Chang, Chun-Yao Huang, Hao-Lin Chiu
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Publication number: 20160098965Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.Type: ApplicationFiled: October 1, 2014Publication date: April 7, 2016Inventors: Hao-Lin Chiu, Byung Duk Yang, Chun-Yao Huang, Kyung Wook Kim, Shih Chang Chang, Szu-Hsien Lee
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Patent number: 9293102Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.Type: GrantFiled: October 1, 2014Date of Patent: March 22, 2016Assignee: Apple, Inc.Inventors: Hao-Lin Chiu, Byung Duk Yang, Chun-Yao Huang, Kyung Wook Kim, Shih Chang Chang, Szu-Hsien Lee
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Patent number: 9018687Abstract: A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern.Type: GrantFiled: June 12, 2014Date of Patent: April 28, 2015Assignee: Au Optronics CorporationInventors: Yih-Chyun Kao, Hao-Lin Chiu, Chun-Nan Lin
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Patent number: 8987049Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.Type: GrantFiled: September 2, 2014Date of Patent: March 24, 2015Assignee: Apple Inc.Inventors: Ming-Chin Hung, Kyung Wook Kim, Young Bae Park, Hao-Lin Chiu, Chun-Yao Huang, Shih Chang Chang
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Publication number: 20140370655Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.Type: ApplicationFiled: September 2, 2014Publication date: December 18, 2014Inventors: Ming-Chin Hung, Kyung Wook Kim, Young Bae Park, Hao-Lin Chiu, Chun-Yao Huang, Shih Chang Chang
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Publication number: 20140291742Abstract: A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern.Type: ApplicationFiled: June 12, 2014Publication date: October 2, 2014Inventors: Yih-Chyun Kao, Hao-Lin Chiu, Chun-Nan Lin
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Patent number: 8823003Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.Type: GrantFiled: September 27, 2012Date of Patent: September 2, 2014Assignee: Apple Inc.Inventors: Ming-Chin Hung, Kyung Wook Kim, Young Bae Park, Hao-Lin Chiu, Chun-Yao Huang, Shih Chang Chang
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Patent number: 8796079Abstract: A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern.Type: GrantFiled: November 21, 2012Date of Patent: August 5, 2014Assignee: Au Optronics CorporationInventors: Yih-Chyun Kao, Hao-Lin Chiu, Chun-Nan Lin
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Patent number: 8723835Abstract: The present application provides a touch-sensing display panel comprising a display panel and a touch-sensing device disposed above the display panel. The touch-sensing device comprises a plurality of select lines, a plurality of readout lines and a plurality of capacitive touch-sensing units arranged in array. Each of the capacitive touch-sensing units comprises a transistor and a touch-sensing pad, each of the transistors comprises a gate electrode electrically connected to one of the select lines, a source electrode electrically connected to a reference voltage, a drain electrode electrically connected to one of the readout lines, and a channel layer electrically coupled to the touch-sensing pad.Type: GrantFiled: November 30, 2010Date of Patent: May 13, 2014Assignee: Au Optronics CorporationInventors: Hao-Lin Chiu, Chun-Yao Huang, Yih-Chyun Kao, Ya-Hsiang Tai, Lu-Sheng Chou, Kuan-Da Lin
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Patent number: 8704220Abstract: An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes.Type: GrantFiled: April 12, 2012Date of Patent: April 22, 2014Assignee: Au Optronics CorporationInventors: Hao-Lin Chiu, Chi-Jui Lin, Shu-Wei Tsao, Chun-Nan Lin, Po-Liang Yeh, Shine-Kai Tseng
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Patent number: 8698150Abstract: An active device, a driving circuit structure, and a display panel are provided. The active device includes a gate, a gate insulation layer covering the gate, a semiconductor layer disposed above the gate, an etching stop layer disposed on the gate insulation layer and the semiconductor layer, a source, and a drain. The gate forms a meandering pattern on a substrate. The semiconductor layer has an area substantially defining a device region where the active device is. The etching stop layer has a first contact opening and a second contact opening. The first contact opening and the second contact opening separated from each other and both exposing the semiconductor layer. The source and the drain separated from each other are disposed on the etching stop layer and in contact with the semiconductor layer through the first contact opening and the second contact opening, respectively.Type: GrantFiled: October 4, 2012Date of Patent: April 15, 2014Assignee: Au Optronics CorporationInventors: Chao-Yu Yang, Hao-Lin Chiu, Shu-Wei Tsao, Shih-Che Huang, Po-Liang Yeh, Chun-Nan Lin, Shine-Kai Tseng
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Publication number: 20140042427Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.Type: ApplicationFiled: September 27, 2012Publication date: February 13, 2014Applicant: Apple Inc.Inventors: Ming-Chin Hung, Kyung Wook Kim, Young Bae Park, Hao-Lin Chiu, Chun-Yao Huang, Shih Chang Chang
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Publication number: 20130328069Abstract: An active device, a driving circuit structure, and a display panel are provided. The active device includes a gate, a gate insulation layer covering the gate, a semiconductor layer disposed above the gate, an etching stop layer disposed on the gate insulation layer and the semiconductor layer, a source, and a drain. The gate forms a meandering pattern on a substrate. The semiconductor layer has an area substantially defining a device region where the active device is. The etching stop layer has a first contact opening and a second contact opening. The first contact opening and the second contact opening separated from each other and both exposing the semiconductor layer. The source and the drain separated from each other are disposed on the etching stop layer and in contact with the semiconductor layer through the first contact opening and the second contact opening, respectively.Type: ApplicationFiled: October 4, 2012Publication date: December 12, 2013Applicant: AU OPTRONICS CORPORATIONInventors: Chao-Yu Yang, Hao-Lin Chiu, Shu-Wei Tsao, Shih-Che Huang, Po-Liang Yeh, Chun-Nan Lin, Shine-Kai Tseng
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Publication number: 20130119371Abstract: An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes.Type: ApplicationFiled: April 12, 2012Publication date: May 16, 2013Applicant: AU OPTRONICS CORPORATIONInventors: Hao-Lin Chiu, Chi-Jui Lin, Shu-Wei Tsao, Chun-Nan Lin, Po-Liang Yeh, Shine-Kai Tseng