Patents by Inventor Hao-Lin Chiu

Hao-Lin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160321975
    Abstract: A display may have a first stage such as a color liquid crystal display stage and a second stage such as a monochromatic liquid crystal display stage that are coupled in tandem so that light from a backlight passes through both stages. The pixel pitch of the second stage may be greater than the pixel pitch of the first stage to ease alignment tolerances and reduce image processing complexity. The first stage may be provided with straight black masking strips, whereas the second stage may be provided with angled zigzagging black masking strips. The angle of the zigzagging black masking strips and the ratio of the pixel pitch of the second stage to that of the first stage may be selected to maximize optical transmittance while minimizing Moire effects.
    Type: Application
    Filed: September 23, 2015
    Publication date: November 3, 2016
    Inventors: Jin Yan, Young Cheol Yang, Jun Jiang, Hao-Lin Chiu, Young-Jik Jo, Cheng Chen
  • Publication number: 20160098965
    Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 7, 2016
    Inventors: Hao-Lin Chiu, Byung Duk Yang, Chun-Yao Huang, Kyung Wook Kim, Shih Chang Chang, Szu-Hsien Lee
  • Publication number: 20160098144
    Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.
    Type: Application
    Filed: October 26, 2015
    Publication date: April 7, 2016
    Inventors: Byung Duk Yang, Szu-Hsien Lee, Kyung Wook Kim, Shih Chang Chang, Chun-Yao Huang, Hao-Lin Chiu
  • Patent number: 9293102
    Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: March 22, 2016
    Assignee: Apple, Inc.
    Inventors: Hao-Lin Chiu, Byung Duk Yang, Chun-Yao Huang, Kyung Wook Kim, Shih Chang Chang, Szu-Hsien Lee
  • Patent number: 9018687
    Abstract: A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: April 28, 2015
    Assignee: Au Optronics Corporation
    Inventors: Yih-Chyun Kao, Hao-Lin Chiu, Chun-Nan Lin
  • Patent number: 8987049
    Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: March 24, 2015
    Assignee: Apple Inc.
    Inventors: Ming-Chin Hung, Kyung Wook Kim, Young Bae Park, Hao-Lin Chiu, Chun-Yao Huang, Shih Chang Chang
  • Publication number: 20140370655
    Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.
    Type: Application
    Filed: September 2, 2014
    Publication date: December 18, 2014
    Inventors: Ming-Chin Hung, Kyung Wook Kim, Young Bae Park, Hao-Lin Chiu, Chun-Yao Huang, Shih Chang Chang
  • Publication number: 20140291742
    Abstract: A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern.
    Type: Application
    Filed: June 12, 2014
    Publication date: October 2, 2014
    Inventors: Yih-Chyun Kao, Hao-Lin Chiu, Chun-Nan Lin
  • Patent number: 8823003
    Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: September 2, 2014
    Assignee: Apple Inc.
    Inventors: Ming-Chin Hung, Kyung Wook Kim, Young Bae Park, Hao-Lin Chiu, Chun-Yao Huang, Shih Chang Chang
  • Patent number: 8796079
    Abstract: A fabrication method of a pixel structure and a pixel structure are provided. A first patterned metal layer including scan lines and a gate is formed on a substrate. A first insulation layer, a semiconductor layer, an etching stop pattern and a metal layer are formed sequentially on the first patterned metal layer. The metal layer and the semiconductor layer are patterned to form a second patterned metal layer and a patterned semiconductor layer. The second patterned metal layer includes data lines, a source and a drain. The patterned semiconductor layer includes a first semiconductor pattern completely overlapping the second patterned metal layer and a second semiconductor pattern without overlapping the second patterned metal layer, wherein the second semiconductor pattern includes a channel pattern and a marginal pattern. The channel pattern is between the source and the drain and the marginal pattern surrounds the first semiconductor pattern.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: August 5, 2014
    Assignee: Au Optronics Corporation
    Inventors: Yih-Chyun Kao, Hao-Lin Chiu, Chun-Nan Lin
  • Patent number: 8723835
    Abstract: The present application provides a touch-sensing display panel comprising a display panel and a touch-sensing device disposed above the display panel. The touch-sensing device comprises a plurality of select lines, a plurality of readout lines and a plurality of capacitive touch-sensing units arranged in array. Each of the capacitive touch-sensing units comprises a transistor and a touch-sensing pad, each of the transistors comprises a gate electrode electrically connected to one of the select lines, a source electrode electrically connected to a reference voltage, a drain electrode electrically connected to one of the readout lines, and a channel layer electrically coupled to the touch-sensing pad.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: May 13, 2014
    Assignee: Au Optronics Corporation
    Inventors: Hao-Lin Chiu, Chun-Yao Huang, Yih-Chyun Kao, Ya-Hsiang Tai, Lu-Sheng Chou, Kuan-Da Lin
  • Patent number: 8704220
    Abstract: An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: April 22, 2014
    Assignee: Au Optronics Corporation
    Inventors: Hao-Lin Chiu, Chi-Jui Lin, Shu-Wei Tsao, Chun-Nan Lin, Po-Liang Yeh, Shine-Kai Tseng
  • Patent number: 8698150
    Abstract: An active device, a driving circuit structure, and a display panel are provided. The active device includes a gate, a gate insulation layer covering the gate, a semiconductor layer disposed above the gate, an etching stop layer disposed on the gate insulation layer and the semiconductor layer, a source, and a drain. The gate forms a meandering pattern on a substrate. The semiconductor layer has an area substantially defining a device region where the active device is. The etching stop layer has a first contact opening and a second contact opening. The first contact opening and the second contact opening separated from each other and both exposing the semiconductor layer. The source and the drain separated from each other are disposed on the etching stop layer and in contact with the semiconductor layer through the first contact opening and the second contact opening, respectively.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: April 15, 2014
    Assignee: Au Optronics Corporation
    Inventors: Chao-Yu Yang, Hao-Lin Chiu, Shu-Wei Tsao, Shih-Che Huang, Po-Liang Yeh, Chun-Nan Lin, Shine-Kai Tseng
  • Publication number: 20140042427
    Abstract: A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.
    Type: Application
    Filed: September 27, 2012
    Publication date: February 13, 2014
    Applicant: Apple Inc.
    Inventors: Ming-Chin Hung, Kyung Wook Kim, Young Bae Park, Hao-Lin Chiu, Chun-Yao Huang, Shih Chang Chang
  • Publication number: 20130328069
    Abstract: An active device, a driving circuit structure, and a display panel are provided. The active device includes a gate, a gate insulation layer covering the gate, a semiconductor layer disposed above the gate, an etching stop layer disposed on the gate insulation layer and the semiconductor layer, a source, and a drain. The gate forms a meandering pattern on a substrate. The semiconductor layer has an area substantially defining a device region where the active device is. The etching stop layer has a first contact opening and a second contact opening. The first contact opening and the second contact opening separated from each other and both exposing the semiconductor layer. The source and the drain separated from each other are disposed on the etching stop layer and in contact with the semiconductor layer through the first contact opening and the second contact opening, respectively.
    Type: Application
    Filed: October 4, 2012
    Publication date: December 12, 2013
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Chao-Yu Yang, Hao-Lin Chiu, Shu-Wei Tsao, Shih-Che Huang, Po-Liang Yeh, Chun-Nan Lin, Shine-Kai Tseng
  • Publication number: 20130119371
    Abstract: An active device including a source, a drain, an oxide semiconductor layer, a gate and a gate insulator layer is provided. The source includes first stripe electrodes parallel to each other and a first connection electrode connected thereto. The drain includes second stripe electrodes parallel to each other and a second connection electrode connected thereto, wherein the first stripe electrodes and the second stripe electrodes are parallel to each other, electrically isolated, and alternately arranged, and a zigzag trench is formed therebetween. The gate extends along the zigzag trench. The oxide semiconductor layer is in contact with the source and drain, wherein a contact area among the oxide semiconductor layer and each first stripe electrodes substantially equals to a layout area of each first stripe electrodes and a contact area among each second stripe electrodes substantially equals to a layout area of each second stripe electrodes.
    Type: Application
    Filed: April 12, 2012
    Publication date: May 16, 2013
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Hao-Lin Chiu, Chi-Jui Lin, Shu-Wei Tsao, Chun-Nan Lin, Po-Liang Yeh, Shine-Kai Tseng
  • Publication number: 20120287075
    Abstract: The invention discloses an active matrix touch sensing circuit apparatus used in a touch panel comprises a sensing unit, a resistance, and a thin film transistor. The resistance connects the sensing unit and the first scan line. The control end of the thin film transistor connects the sensing unit, the second scan line connects the input end of the thin film transistor, and the read out line connects the output end of the thin film transistor. When the sensing value of the body touch sensing unit is changed, and then the input wave form of the control end is changed. The output end generates an open current, and the read out line transmits the open current.
    Type: Application
    Filed: June 29, 2011
    Publication date: November 15, 2012
    Applicant: National Chiao Tung University
    Inventors: Ya-Hsiang Tai, Lu-Sheng Chou, Hao-Lin Chiu
  • Publication number: 20120133607
    Abstract: The present application provides a touch-sensing display panel comprising a display panel and a touch-sensing device disposed above the display panel. The touch-sensing device comprises a plurality of select lines, a plurality of readout lines and a plurality of capacitive touch-sensing units arranged in array. Each of the capacitive touch-sensing units comprises a transistor and a touch-sensing pad, each of the transistors comprises a gate electrode electrically connected to one of the select lines, a source electrode electrically connected to a reference voltage, a drain electrode electrically connected to one of the readout lines, and a channel layer electrically coupled to the touch-sensing pad.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Hao-Lin Chiu, Chun-Yao Huang, Yih-Chyun Kao, Ya-Hsiang Tai, Lu-Sheng Chou, Kuan-Da Lin
  • Publication number: 20120026072
    Abstract: A display panel, a repair method, and an active device array substrate including a substrate, first and second signal lines, active devices, pixel electrodes, a bus line, and a switch device are provided. The bus line and the switch device are disposed outside a display region of the active device array substrate. The switch device has a gate coupled to the bus line, a first electrode coupled to a signal source, and a second electrode coupled to one of the first signal lines. The first and second electrodes are comb-shaped. The first electrode includes first fingers parallel to one another and a first connection portion connected to the first fingers. The second electrode includes second fingers parallel to one another and a second connection portion connected to the second fingers. The first and second fingers are arranged alternately. A portion of the first electrode is located outside the gate.
    Type: Application
    Filed: October 6, 2010
    Publication date: February 2, 2012
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Hao-Lin Chiu, Yih-Chyun Kao