Abstract: A chipset implemented in a server node of a server system and including an embedded management controller (eMC) is disclosed. The eMC collects inner-node information of the server node for server system management. The eMC is coupled to a baseboard management controller (BMC) that is outside the server node and communicates with a remote console through a network. The eMC is specially designed for the corresponding server node to be differentiated from the other server nodes also coupled to the BMC. All eMCs coupled to the same BMC boot in a special way.

Abstract: A chipset implemented in a server node of a server system and including an embedded management controller is disclosed. The chipset also includes a northbridge and southbridge. The embedded management controller collects inner-node information of the server node for server system management. The embedded management controller is coupled to a baseboard management controller, and the baseboard management controller is outside the server node and communicates with a remote console through network.

Abstract: A chipset implemented in a server node of a server system and including an embedded management controller is disclosed. The chipset also includes a northbridge and southbridge. The embedded management controller collects inner-node information of the server node for server system management. The embedded management controller is coupled to a baseboard management controller, and the baseboard management controller is outside the server node and communicates with a remote console through network.

Abstract: A computer system with integrated storage device for storing both a basic input/output system (BIOS) code and an operating system (OS) code and an associated booting method are provided. The computer system includes a central processing unit, a storage device controller and the storage device. The BIOS code and the OS code are stored in an invisible are and a visible area of the storage device, respectively. At first, the storage device controller is activated to read data from an architecture information area of the storage device to perform initialization. Then, the initialized storage device controller converts a read-only memory access command issued from the central processing unit into a suitable format to control loading of the BIOS code from the invisible area. At last, the storage device controller controls loading of the OS code from the visible area to finish the booting of the computer system.

Abstract: An embodiment of a computer system comprises a south-bridge. The south-bridge comprises a controller including a buffer for communicating with electronic devices. When detecting that a Reset# signal is asserted, the buffer is set to a Hi-Impedance state to separate the controller from the electronic device. The Reset# signal indicates a full system reset.

Abstract: A computer system is provided. The computer system includes a bus, a first master device, a second master device and a processor. The bus has a data line and a clock line. The first master device is coupled to the bus, detects a start phase of a first transaction on the data line, issues an interrupt message upon the detection of the start phase, and triggers a second transaction in response to a transaction indication message. The processor is coupled to the first master device, receives the interrupt message, and transmits the transaction indication message after a predetermined time interval upon reception of the interrupt message. The second master device is coupled to the bus and triggers the first transaction. The first transaction is finished within the predetermined time interval.

Abstract: A computer system is provided. The computer system includes a bus, a first master device, a second master device and a processor. The bus has a data line and a clock line. The first master device is coupled to the bus, detects a start phase of a first transaction on the data line, issues an interrupt message upon the detection of the start phase, and triggers a second transaction in response to a transaction indication message. The processor is coupled to the first master device, receives the interrupt message, and transmits the transaction indication message after a predetermined time interval upon reception of the interrupt message. The second master device is coupled to the bus and triggers the first transaction. The first transaction is finished within the predetermined time interval.

Abstract: A computer system with integrated storage device for storing both a basic input/output system (BIOS) code and an operating system (OS) code and an associated booting method are provided. The computer system includes a central processing unit, a storage device controller and the storage device. The BIOS code and the OS code are stored in an invisible are and a visible area of the storage device, respectively. At first, the storage device controller is activated to read data from an architecture information area of the storage device to perform initialization. Then, the initialized storage device controller converts a read-only memory access command issued from the central processing unit into a suitable format to control loading of the BIOS code from the invisible area. At last, the storage device controller controls loading of the OS code from the visible area to finish the booting of the computer system.

Abstract: Thermal throttling duty estimation methods for a CPU (Central Processing Unit) in a computer system are provided. The temperature of a CPU is highly related to the CPU performance. CPU temperature data (CPUT) is first acquired. A thermal throttle duty (TTD) is then calculated according to the acquired CPUT. Thereafter, the calculated TTD can be sent to the CPU and the CPU performance is accordingly adjusted.

Abstract: A power saving method and system thereof is disclosed. When the central processing unit is under a non-snooping sleep state and a peripheral device sends a bus master request, a chip will drive the central processing unit waking from the non-snooping sleep state and entering a system management mode for executing an interrupt service routine that makes the central processing unit in halt status. The central processing unit is then driven to enter a snooping sleep state for snooping the bus master request. After the execution of the bus master request, the chip will drive the central processing unit to leave the snooping sleep state and return to the non-snooping sleep state for power consumption conservation.

Abstract: An embodiment of a computer system comprises a south-bridge. The south-bridge comprises a controller including a buffer for communicating with electronic devices. When detecting that a Reset# signal is asserted, the buffer is set to a Hi-Impedance state to separate the controller from the electronic device. The Reset# signal indicates a full system reset.

Abstract: A method for capturing an image data from a frame buffer of a computer system takes advantage of a system management interrupt service optionally triggered. If a storage unit functions normally when the computer system fails to work normally, store the image data in the frame buffer into the storage unit. Otherwise, temporarily store the image data in a buffer unit, and then store it in a NVRAM. Then restart the storage unit and restore the image data in the buffer unit into the storage unit. At last, restart the computer system.

Abstract: A debugging device and method are provided, including a central processing unit (CPU) connected to a chipset with a system management interrupt pin. The debugging method includes sending out a system management interrupt signal to central processing unit from the system management interrupt pin of the chipset. Then the CPU moves into a system management mode and pops out a debugging operation window for selecting and executing each debugging item. After the execution of each debugging item is completed, the CPU will leave the debugging operation window and return to the next instruction before debugging. After the execution of each debugging item is completed in the debugging operation window, the CPU will return to the operation system and continue the execution of next instruction before debugging. The execution of debugging will not influence the status and the program execution from the operating system. The disclosed debugging method is convenient for executing each debugging item at any time.

Abstract: Thermal throttling duty estimation methods for a CPU (Central Processing Unit) in a computer system are provided. The temperature of a CPU is highly related to the CPU performance. CPU temperature data (CPUT) is first acquired. A thermal throttle duty (TTD) is then calculated according to the acquired CPUT. Thereafter, the calculated TTD can be sent to the CPU and the CPU performance is accordingly adjusted.

Abstract: A device information management system comprises an application device and a BIOS ROM. The BIOS ROM comprises at least one specific region storing device information for the application device. The specific region is not used by a BIOS and not within a calculation range for checksum calculation. The BIOS ROM further comprises an index recording an address of the specific region. The application device reads the index from the BIOS ROM, and reads the device information from the specific region according to the index.

Abstract: A method for accessing a memory of a computer system for BIOS codes optionally performs a detection procedure to realize a maximum memory burst read size of the memory according to a flag value upon the computer system is initialized. For example, the detection procedure is performed when the flag value is logic “1” and the detection procedure is not performed when the flag value is logic “0”. When the detection procedure is performed, read requests with sequentially reduced memory burst read sizes are asserted to the memory one by one until the maximum memory burst read size of the memory is realized. Then, the BIOS codes are read from the memory with the maximum memory burst read size.

Abstract: A debugging device and method are provided, including a central processing unit (CPU) connected to a chipset with a system management interrupt pin. The debugging method includes sending out a system management interrupt signal to central processing unit from the system management interrupt pin of the chipset. Then the CPU moves into a system management mode and pops out a debugging operation window for selecting and executing each debugging item. After the execution of each debugging item is completed, the CPU will leave the debugging operation window and return to the next instruction before debugging. After the execution of each debugging item is completed in the debugging operation window, the CPU will return to the operation system and continue the execution of next instruction before debugging. The execution of debugging will not influence the status and the program execution from the operating system. The disclosed debugging method is convenient for executing each debugging item at any time.