Patents by Inventor Hao Nham

Hao Nham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160371411
    Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 22, 2016
    Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
  • Publication number: 20160292343
    Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.
    Type: Application
    Filed: April 2, 2015
    Publication date: October 6, 2016
    Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
  • Publication number: 20160292316
    Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.
    Type: Application
    Filed: April 3, 2015
    Publication date: October 6, 2016
    Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
  • Publication number: 20160292314
    Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.
    Type: Application
    Filed: April 3, 2015
    Publication date: October 6, 2016
    Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
  • Publication number: 20160292313
    Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.
    Type: Application
    Filed: April 3, 2015
    Publication date: October 6, 2016
    Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
  • Publication number: 20160292317
    Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.
    Type: Application
    Filed: April 3, 2015
    Publication date: October 6, 2016
    Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
  • Publication number: 20160292315
    Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.
    Type: Application
    Filed: April 3, 2015
    Publication date: October 6, 2016
    Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
  • Patent number: 9460256
    Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: October 4, 2016
    Assignee: eSilicon Corporation
    Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
  • Patent number: 9460257
    Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: October 4, 2016
    Assignee: eSilicon Corporation
    Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
  • Patent number: 9460254
    Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: October 4, 2016
    Assignee: eSilicon Corporation
    Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
  • Patent number: 9460255
    Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: October 4, 2016
    Assignee: eSilicon Corporation
    Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
  • Patent number: 9454628
    Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: September 27, 2016
    Assignee: eSilicon Corporation
    Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell
  • Patent number: 9454636
    Abstract: In one aspect, a method for providing design point recommendations for an integrated circuit (IC) design is disclosed. The method comprises receiving an IC design along with a reference PPA (power, performance, area) metric at a reference design point, and a target PPA metric. The method also comprises estimating trial PPA metrics for the IC design at multiple design points, wherein estimating trial PPA metric at each design point includes accessing a PPA database containing PPA metrics for multiple test components, determining scale factors from the reference design point to the trial design point for test components equivalent to components of the IC design, and applying the scale factors to the reference PPA metric to determine the trial PPA metric for the trial design point. The method further comprises recommending a trial design point based on the estimated trial PPA metric and the received target PPA metric.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: September 27, 2016
    Assignee: eSilicon Corporation
    Inventors: Prasad Subramaniam, Hao Nham, Rakesh Chadha, Ferran Martorell