Abstract: A target device includes: a first tray located at a bottom of the target device; at least one second tray located above the first tray; and a damping resonator detachably installed in the first tray. A resonance frequency acquisition device is disposed in the at least one second tray configured to obtain a target resonance frequency of the target device, and the damping resonator is configured to suppress a resonance response of the target device at the target resonance frequency.

Abstract: A method for controlling a beam in a cell, includes obtaining traffic distribution data of a plurality of beam areas included in the cell, obtaining a total number of a plurality of beams for a beam area among the plurality of the beam areas, based on the obtained traffic distribution data, and obtaining a beam width of one among the plurality of beams for the beam area, based on the obtained total number of the plurality of beams. The method further includes obtaining, from a candidate beam set, candidate beams for the beam area, based on the obtained total number of the plurality of beams and the obtained beam width of the one among the plurality of beams, and obtaining, from the obtained candidate beams, multiple beams for the beam area, based on a distance between the obtained candidate beams and the beam area.

Abstract: An apparatus for beam configuration in a wireless communication system, including a transceiver; and at least one processor connected with the transceiver and configured to: form at least one beam cluster from beams of a base station; determine a configuration of the at least one beam cluster; and configure the beams in the at least one beam cluster according to the determined configuration

Abstract: A magnetic memory and its programming control method and reading method, and a magnetic storage device of the magnetic memory are provided in the present disclosure. The magnetic memory includes a first magnetic tunnel junction memory cell, including a first terminal coupled to a first bit line, and further includes a switch device, including a first terminal coupled to a second terminal of the first magnetic tunnel junction memory cell, and a control terminal connected to a switch control signal. The magnetic memory further includes a second magnetic tunnel junction memory cell, including a first terminal coupled to a second bit line, and a second terminal coupled to a second terminal of the switch device. The magnetic memory further includes a first transistor, a second transistor, and a sensing amplifier.

Abstract: Readout circuit and magnetic memory are provided. The readout circuit includes a first charging capacitor with one end grounded and another end coupled to an output of a data unit; a first pre-charge module for charging the first charging capacitor; a first discharge control module for controlling a magnitude of a data voltage; a second charging capacitor with one end grounded and another end coupled to an output of a reference unit; a second pre-charge module for charging the second charging capacitor; a second discharge control module for controlling a magnitude of a reference voltage; and a sense amplifier for outputting readout signals.

Abstract: A method for controlling a beam in a cell, includes obtaining traffic distribution data of a plurality of beam areas included in the cell, obtaining a total number of a plurality of beams for a beam area among the plurality of the beam areas, based on the obtained traffic distribution data, and obtaining a beam width of one among the plurality of beams for the beam area, based on the obtained total number of the plurality of beams. The method further includes obtaining, from a candidate beam set, candidate beams for the beam area, based on the obtained total number of the plurality of beams and the obtained beam width of the one among the plurality of beams, and obtaining, from the obtained candidate beams, multiple beams for the beam area, based on a distance between the obtained candidate beams and the beam area.

Abstract: A data reading circuit and a storage unit are provided. The data reading circuit includes a being read unit, a reference current generation unit, a current adjustment unit, a reference unit, a comparison unit, and a voltage stabilization unit corresponding to the reference unit. The being read unit is connected to the current adjustment unit and the comparison unit. The reference current generation unit is connected to the current adjustment unit. The current adjustment unit is connected to the reference current generation unit, the being read unit, and the comparison unit. The reference unit is connected to the voltage stabilization unit. The comparison unit is connected to the voltage stabilization unit, the being read unit, and the current adjustment unit. The voltage stabilization unit is connected to the reference unit and the comparison unit.

Abstract: An apparatus for beam configuration in a wireless communication system, including a transceiver; and at least one processor connected with the transceiver and configured to: form at least one beam cluster from beams of a base station; determine a configuration of the at least one beam cluster; and configure the beams in the at least one beam cluster according to the determined configuration

Abstract: A magnetic memory and its programming control method and reading method, and a magnetic storage device of the magnetic memory are provided in the present disclosure. The magnetic memory includes a first magnetic tunnel junction memory cell, including a first terminal coupled to a first bit line, and further includes a switch device, including a first terminal coupled to a second terminal of the first magnetic tunnel junction memory cell, and a control terminal connected to a switch control signal. The magnetic memory further includes a second magnetic tunnel junction memory cell, including a first terminal coupled to a second bit line, and a second terminal coupled to a second terminal of the switch device. The magnetic memory further includes a first transistor, a second transistor, and a sensing amplifier.

Abstract: A data reading circuit and a storage unit are provided. The data reading circuit includes a being read unit, a reference current generation unit, a current adjustment unit, a reference unit, a comparison unit, and a voltage stabilization unit corresponding to the reference unit. The being read unit is connected to the current adjustment unit and the comparison unit. The reference current generation unit is connected to the current adjustment unit. The current adjustment unit is connected to the reference current generation unit, the being read unit, and the comparison unit. The reference unit is connected to the voltage stabilization unit. The comparison unit is connected to the voltage stabilization unit, the being read unit, and the current adjustment unit. The voltage stabilization unit is connected to the reference unit and the comparison unit.

Abstract: Readout circuit and magnetic memory are provided. The readout circuit includes a first charging capacitor with one end grounded and another end coupled to an output of a data unit; a first pre-charge module for charging the first charging capacitor; a first discharge control module for controlling a magnitude of a data voltage; a second charging capacitor with one end grounded and another end coupled to an output of a reference unit; a second pre-charge module for charging the second charging capacitor; a second discharge control module for controlling a magnitude of a reference voltage; and a sense amplifier for outputting readout signals.

Abstract: The present disclosure provides a scheduling method, a coordinated-transmission node and a CCN for downlink coordinated-transmission. The scheduling method at a coordinated-transmission node side includes: receiving, by a coordinated-transmission node, scheduling privilege information corresponding to a downlink time-frequency resource from a CCN, the scheduling privilege information corresponding to the downlink time-frequency resource indicating a scheduling privilege of the coordinated-transmission node over the downlink time-frequency resource; and performing, by the coordinated-transmission node, the scheduling in accordance with the received scheduling privilege information and the latest CSI reported by the terminal.

Abstract: A non-volatile memory (NVM) includes at least one memory unit region, each including a memory array and having first memory cells in the odd columns and second memory cells in the even columns. Corresponding to each memory unit region, the NVM includes a multiplexer including first bit line decoders and second bit line decoders, a comparator circuit including a first input terminal and a second input terminal, and a bias generation circuit generating a bias voltage. When reading a data information from a first memory cell, a first output voltage of the first memory cell is sent to the first input terminal and the bias voltage is sent to the second input terminal. When reading a data information from a second memory cell, a second output voltage of the second memory cell is sent to the second input terminal and the bias voltage is sent to the first input terminal.

Abstract: A high voltage level shifting circuit and related semiconductor devices are presented. The circuit comprises: a level conversion circuit that converts an input signal with a first high voltage to an output signal with a second high voltage; a first switch having a first node connected to a first power source and a second node connected to a control node of a first transistor; a second switch having a first node connected to the control node of the first transistor and a second node connected to a first connection node; and a switch control circuit connected to the first switch and the second switch and controls them not to be close at the same time. By adding these two switches to the level conversion circuit, this inventive concept substantially lowers the static current generated during a high voltage level conversion process.

Abstract: The embodiments of the present application relate to the technical field of wireless communications, and in particular, to a method, system and device for scheduling a resource, which are used for solving the problems that the realization of non-central coordinated scheduling using an iterative method needs to perform iterative scheduling information interaction, and scheduling time delay will obviously increase in the case of a relatively large X2 interface time delay in the prior art.

Abstract: Memory arrays and reading, programming and erasing methods of the memory arrays are provided. An exemplary memory array includes a plurality of memory columns. Each memory column has a plurality of flash memory cells. The memory columns are divided into at least two blocks. At least one source pull down column is disposed between the two adjacent blocks. Each source pull down column has a plurality of flash memory cells. A source of each flash memory cell in the source pull down column is coupled to sources of the flash memory cells of the plurality memory columns in a same row as the flash memory cell in the source pull down column to pull down a source of a selected flash memory cell to 0 V.

Abstract: A high voltage level shifting circuit and related semiconductor devices are presented. The circuit comprises: a level conversion circuit that converts an input signal with a first high voltage to an output signal with a second high voltage; a first switch having a first node connected to a first power source and a second node connected to a control node of a first transistor; a second switch having a first node connected to the control node of the first transistor and a second node connected to a first connection node; and a switch control circuit connected to the first switch and the second switch and controls them not to be close at the same time. By adding these two switches to the level conversion circuit, this inventive concept substantially lowers the static current generated during a high voltage level conversion process.

Abstract: A memory decoding system includes a memory decoding reference current module. The memory decoding reference current module includes: a first reference current unit connected to one end of a second reference bit line; a second reference current unit connected to one end of a first reference bit line; a third reference current unit connected to one end of a third reference bit line; a first reference NMOS transistor, a source of which is connected to the second reference bit line; a second reference NMOS transistor, a source of which is connected to a drain of the first reference NMOS transistor; and a gate of the first reference NMOS transistor and a gate of the second NMOS transistor are connected to a logic high level.