Patents by Inventor Hao Pan

Hao Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230022100
    Abstract: A machine-learning-based prognostic and health management system comprises a machine sensor, an instruction receiver, a processor, and an annunciator. The machine sensor is configured to dynamically receive data of a machine under test associated with operations of the machine under test. The instruction receiver is configured to dynamically receive a model-assigning command. The processor is configured to dynamically apply a damage alert machine-learning model corresponding to the model-assigning command for processing the data of the machine under test to predict an anomaly probability of an anomaly occurrence of the machine under test. The processor also dynamically generates, according to the anomaly probability, a damage possibility warning on the machine under test, and determine whether to keep the machine under test running or not.
    Type: Application
    Filed: July 12, 2022
    Publication date: January 26, 2023
    Inventors: MENG-JEN CHEN, YEN-JEN CHEN, YUAN-HAO WEN, YING-HAO PAN
  • Patent number: 11563009
    Abstract: A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0×10?4 ?cm to 1.0×104 ?cm or a sheet resistance in a range from 1.0×102?/? to 1.0×1010?/?.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 24, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jenn-Gwo Hwu, Samuel C. Pan, Chien-Shun Liao, Kuan-Hao Tseng
  • Patent number: 11563106
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The formation method includes forming a fin structure over a semiconductor substrate and forming a first isolation feature in the fin structure. The formation method also includes forming a second isolation feature over the semiconductor substrate after the formation of the first isolation feature. The fin structure and the first isolation feature protrude from the second isolation feature. The formation method further includes forming gate stacks over the second isolation feature, wherein the gate stacks surround the fin structure and the first isolation feature.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: January 24, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Shi-Ning Ju, Kuan-Ting Pan, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20230016577
    Abstract: An integrated circuit and method of making an integrated circuit is provided. The integrated circuit includes an electrically conductive pad having a generally planar top surface that includes a cavity having a bottom surface and sidewalls extending from the bottom surface of the cavity to the top surface of the pad. An electronic device is attached to the top surface of the electrically conductive pad. A wire bond is attached from the electronic device to the bottom surface of the cavity. A molding compound encapsulates the electronic device.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 19, 2023
    Inventors: Bo-Hsun Pan, Hung-Yu Chou, Chung-Hao Lin, Yuh-Harng Chien
  • Publication number: 20230014998
    Abstract: A device includes a substrate, a first semiconductor channel over the substrate, a second semiconductor channel over the substrate and laterally offset from the first semiconductor channel, and a third semiconductor channel over the substrate and laterally offset from the second semiconductor channel. A first gate structure, a second gate structure, and a third gate structure are over and lateral surround the first, second, and third semiconductor channels, respectively. A first inactive fin is between the first gate structure and the second gate structure, and a second inactive fin is between the second gate structure and the third gate structure. A bridge conductor layer is over the first, second, and third gate structures, and the first and second inactive fins. A dielectric plug extends from an upper surface of the second inactive fin, through the bridge conductor layer, to at least an upper surface of the bridge conductor layer.
    Type: Application
    Filed: July 19, 2021
    Publication date: January 19, 2023
    Inventors: Shi-Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG, Kuan-Lun CHENG, Guan-Lin CHEN, Kuan-Ting PAN
  • Publication number: 20230009707
    Abstract: A video encoding system in which pixel data is decomposed into frequency bands prior to encoding. The frequency bands for a slice of a frame may be buffered so that complexity statistics may be calculated across the frequency bands prior to encoding. The statistics may then be used by a rate control component in determining quantization parameters for the frequency bands for modulating the rate in the encoder for the current slice. The quantization parameters for the frequency bands may be calculated jointly to optimize the quality of the displayed frames after decoder reconstruction and wavelet synthesis on a receiving device. Information about one or more previously processed frames may be used in combination with the statistics for a current slice in determining the quantization parameters for the current slice.
    Type: Application
    Filed: September 16, 2022
    Publication date: January 12, 2023
    Applicant: Apple Inc.
    Inventors: Hao Pan, Jim C. Chou, Felix C. Fernandes
  • Publication number: 20230006051
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure also includes a gate structure including a first portion wrapping around the first nanostructures and a second portion wrapping around the second nanostructures. The semiconductor structure also includes a dielectric feature sandwiched between the first portion and the second portion of the gate structure. In addition, the dielectric feature includes a bottom portion and a top portion over the bottom portion, and the top portion of the dielectric feature includes a shell layer and a core portion surrounded by the shell layer.
    Type: Application
    Filed: January 20, 2022
    Publication date: January 5, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Yi-Ruei JHAN, Shi-Ning JU, Chih-Hao WANG
  • Publication number: 20220415737
    Abstract: A semiconductor device includes semiconductor dies and a redistribution structure. The semiconductor dies are encapsulated in an encapsulant. The redistribution structure extends on the encapsulant and electrically connects the semiconductor dies. The redistribution structure includes dielectric layers and redistribution conductive layers alternately stacked. An outermost dielectric layer of the dielectric layers further away from the semiconductor dies is made of a first material. A first dielectric layer of the dielectric layers on which the outermost dielectric layer extends is made of a second material different from the first material. The first material includes at least one material selected from the group consisting of an epoxy resin, a phenolic resin, a polybenzooxazole, and a polyimide having a curing temperature lower than 250° C.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chieh Wu, Ting Hao Kuo, Kuo-Lung Pan, Po-Yuan Teng, Yu-Chia Lai, Shu-Rong Chun, Mao-Yen Chang, Wei-Kang Hsieh, Pavithra Sriram, Hao-Yi Tsai, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
  • Publication number: 20220412609
    Abstract: Disclosed are a carbon dioxide overlapping type heating system and a control method therefor. The heating system comprises a low-temperature stage loop, a high-temperature stage loop and a heat supply loop, wherein a low-temperature stage compressor (3) and a high-temperature stage compressor (7) are both variable-frequency compressors; and a water pump (10) is a variable-frequency water pump.
    Type: Application
    Filed: December 3, 2019
    Publication date: December 29, 2022
    Inventors: Hao Pan, Xiaoliang Tang, Dan Xiong, Jun You, Qiang Kang, Xiaofei Song
  • Patent number: 11538735
    Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: December 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Rong Chun, Kuo Lung Pan, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chen-Hua Yu
  • Patent number: 11532732
    Abstract: A method includes forming a semiconductor fin extruding from a substrate; forming a sacrificial capping layer on sidewalls of the semiconductor fin; forming first and second dielectric fins sandwiching the semiconductor fin; forming a sacrificial gate stack over the semiconductor fin, the sacrificial capping layer, and the first and second dielectric fins; forming gate spacers on sidewalls of the sacrificial gate stack; removing the sacrificial gate stack to form a gate trench, wherein the gate trench exposes the semiconductor fin, the sacrificial capping layer, and the first and second dielectric fins; removing the sacrificial capping layer from the gate trench, thereby exposing the sidewalls of the semiconductor fin; and forming a metal gate stack in the gate trench engaging the semiconductor fin.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Ruei Jhan, Kuan-Ting Pan, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11532725
    Abstract: Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Shi Ning Ju, Yi-Ruei Jhan, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20220399231
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures and a first dielectric feature separating the gate structure into a first portion and a second portion. The semiconductor structure also includes a metal layer formed over the gate structure. In addition, top surfaces of the first portion and the second portion of the gate structure and a top surface of the first dielectric feature are covered by the metal layer.
    Type: Application
    Filed: August 6, 2021
    Publication date: December 15, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Kuan-Ting PAN, Shi-Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 11527533
    Abstract: According to one example, a semiconductor structure includes a first set of fin structures, a second set of fin structures, and a dielectric stack positioned between the first set of fin structures and the second set of fin structures. The dielectric stack has a top surface at substantially a same level as top surfaces of the first and second sets of fin structures. The dielectric stack includes a first dielectric material conforming to a bottom and sides of the dielectric stack, a second dielectric material along a top surface of the dielectric stack, and a third dielectric material in a middle of the dielectric stack. The semiconductor structure further includes a gate structure positioned over the first set of fin structures, the second set of fin structures and the dielectric stack.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuan-Ting Pan, Yi-Ruei Jhan, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20220393831
    Abstract: A wireless communication method is described. The method is performed by a user device and comprises: determining a list of one or more reference signals; receiving, during a first time unit, a first signaling that includes a state; determining a relationship between a reference signal corresponding to the state and the list; and determining, based on the relationship, a second time unit associated with the state or the first signaling.
    Type: Application
    Filed: August 15, 2022
    Publication date: December 8, 2022
    Inventors: Shujuan ZHANG, Bo GAO, Zhaohua LU, Hao WU, Chuangxin JIANG, Wenjun YAN, Yu PAN
  • Patent number: 11516999
    Abstract: A lighting experimental system and a lighting experimental method for reducing the ability of the poultry to recognize the red objects are provided, wherein wooden testing box is provided with an opening at the top thereof, a square adjustable light-emitting diode (LED) light source is disposed directly above the opening of the wooden testing box, a first black backdrop is fixedly laid on a surface of each inner wall of four sides of the wooden testing box, a horizontal trough is provided at the bottom of the wooden testing box, a feed box is disposed in the horizontal trough, and the feed box is connected to an electric push rod; two color photographic papers are fixed on an inner wall, directly above the horizontal trough, of the wooden testing box, pressure sensors are disposed between the color photographic papers and the inner wall of the wooden testing box.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: December 6, 2022
    Assignee: ZHEJIANG UNIVERSITY
    Inventors: Jinming Pan, Chenghao Pan, Yuchen Hu, Leshang Bai, Hao Jin
  • Publication number: 20220384429
    Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Ting Pan, Chih-Hao Wang
  • Publication number: 20220379266
    Abstract: A polymer film has a loofah-like structure. It has a fibrous framework structure formed by three-dimensional interwoven and interconnected polymer fibers and a three-dimensional interconnected network pore structure distributed in the fibrous framework structure. The polymer is an organic polymer and the fibrous framework structure is integrally formed by the polymer. The film has a volume porosity of from 50% to 95%. The film is obtained by means of a combination method for atomization pretreatment and non-solvent phase separation. The film can be used in the fields of gas filtration, liquid filtration, oil-water separation, adsorption materials, catalysis, pharmaceutical sustained release materials, anti-adhesion coatings, oil delivery and oil spill interception.
    Type: Application
    Filed: October 27, 2020
    Publication date: December 1, 2022
    Inventors: Yiqun LIU, Jing WANG, Guoyuan PAN, Yang ZHANG, Hao YU
  • Publication number: 20220384411
    Abstract: A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.
    Type: Application
    Filed: August 9, 2022
    Publication date: December 1, 2022
    Inventors: Yu-Chia Lai, Kuo Lung Pan, Hung-Yi Kuo, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 11508665
    Abstract: A method includes forming a plurality of dielectric layers, which processes include forming a first plurality of dielectric layers having first thicknesses, and forming a second plurality of dielectric layers having second thicknesses smaller than the first thicknesses. The first plurality of dielectric layers and the second plurality of dielectric layers are laid out alternatingly. The method further includes forming a plurality of redistribution lines connected to form a conductive path, which processes include forming a first plurality of redistribution lines, each being in one of the first plurality of dielectric layers, and forming a second plurality of redistribution lines, each being in one of the second plurality of dielectric layers.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Yuan Teng, Kuo Lung Pan, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chen-Hua Yu