Abstract: To improve on power and bandwidth limitations associated with conventional feedforward equalizer (FFE) implementations, the present disclosure provides intersymbol interference (ISI) compensation circuits that do not use delay cells common to FFE structures. In one example, the compensation circuit of the present disclosure comprises a two stage amplifier. Each stage of the amplifier is implemented using a differential pair with degeneration. One of the amplifier stages has a transfer function with a zero in the left half of the s-domain, also called the s-plane, and the other amplifier has a transfer function with a zero in the right half of the s-domain. The amplifier stage with the zero in the left half of the s-domain can be used to provide post-cursor ISI compensation, and the amplifier stage with the zero in the right half of the s-domain can be used to provide pre-cursor ISI compensation.

Abstract: To improve on power and bandwidth limitations associated with conventional feedforward equalizer (FFE) implementations, the present disclosure provides intersymbol interference (ISI) compensation circuits that do not use delay cells common to FFE structures. In one example, the compensation circuit of the present disclosure comprises a two stage amplifier. Each stage of the amplifier is implemented using a differential pair with degeneration. One of the amplifier stages has a transfer function with a zero in the left half of the s-domain, also called the s-plane, and the other amplifier has a transfer function with a zero in the right half of the s-domain. The amplifier stage with the zero in the left half of the s-domain can be used to provide post-cursor ISI compensation, and the amplifier stage with the zero in the right half of the s-domain can be used to provide pre-cursor ISI compensation.

Abstract: To improve on power and bandwidth limitations associated with conventional feedforward equalizer (FFE) implementations, the present disclosure provides intersymbol interference (ISI) compensation circuits that do not use delay cells common to FFE structures. In one example, the compensation circuit of the present disclosure comprises a two stage amplifier. Each stage of the amplifier is implemented using a differential pair with degeneration. One of the amplifier stages has a transfer function with a zero in the left half of the s-domain, also called the s-plane, and the other amplifier has a transfer function with a zero in the right half of the s-domain. The amplifier stage with the zero in the left half of the s-domain can be used to provide post-cursor ISI compensation, and the amplifier stage with the zero in the right half of the s-domain can be used to provide pre-cursor ISI compensation.

Abstract: To improve on power and bandwidth limitations associated with conventional feedforward equalizer (FFE) implementations, the present disclosure provides intersymbol interference (ISI) compensation circuits that do not use delay cells common to FFE structures. In one example, the compensation circuit of the present disclosure comprises a two stage amplifier. Each stage of the amplifier is implemented using a differential pair with degeneration. One of the amplifier stages has a transfer function with a zero in the left half of the s-domain, also called the s-plane, and the other amplifier has a transfer function with a zero in the right half of the s-domain. The amplifier stage with the zero in the left half of the s-domain can be used to provide post-cursor ISI compensation, and the amplifier stage with the zero in the right half of the s-domain can be used to provide pre-cursor ISI compensation.

Abstract: A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output.

Abstract: A method for reducing noise in an output of a voltage regulator at frequencies above a closed loop bandwidth, by providing a noise injection path for injecting external noise into the voltage regulator, where the noise injection path becomes active at the frequencies above the closed loop bandwidth, where the noise injection path reduces the noise in the output of the voltage regulator.

Abstract: Described embodiments provide a voltage controlled oscillator (VCO) that includes an operational amplifier (opamp). The opamp has a positive power supply input coupled to a power supply voltage, a negative power supply input coupled to a ground node, an inverting input coupled to a control voltage of the VCO, a noninverting input that receives a feedback signal, and an output providing a transistor control voltage. A transistor having a gate terminal coupled to the output of the opamp, a source terminal coupled to the power supply voltage, and a drain terminal coupled to a resistor coupled to ground, generates an output current. A current mirror generates a mirror current based on the output current. A current controlled oscillator (ICO) is coupled to the current mirror, and sets the frequency of the VCO output signal based upon the mirror current.

Abstract: A method for reducing noise in an output of a voltage regulator at frequencies above a closed loop bandwidth, by providing a noise injection path for injecting external noise into the voltage regulator, where the noise injection path becomes active at the frequencies above the closed loop bandwidth, where the noise injection path reduces the noise in the output of the voltage regulator.