Abstract: An image processing method is provided. The method includes the step of comparing each of the input pixels in an input image to a corresponding buffered pixel in a buffered image, and computing the difference value between the input pixel value of the input pixel and the buffered pixel value of the buffered pixel. The method further includes the step of generating a blended image based on the input pixel values and the corresponding difference values. The method further includes the step of determining whether a criterion associated with the difference value is met, for each of the difference values. The method further includes the step of updating, for each of the buffered pixels in the buffered image, the buffered pixel value based on the corresponding input pixel value if the criterion is met, and keeping the buffered pixel value unchanged if the criterion is not met.

Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.

Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.

Abstract: A semiconductor devices includes a substrate, a power grid structure, and a through via penetrating the substrate. The power grid structure includes: first and second rails extending along a first direction, a conductive wire, a third rail, a conductive via, and a connecting member. The conductive wire is between the first and second rails, and extends along the first direction. The third rail is below the first rail, the second rail and the conductive wire, and extends along a second direction perpendicular to the first direction. The conductive via is between and electrically couples the conductive wire to the third rail. The connecting member is between and electrically couples the first rail to the conductive wire. The through via extends through the substrate and along a third direction perpendicular to the first direction and the second direction. The through via is disposed on and coupled to the conductive wire.

Abstract: An image processing method is provided. The method includes a first MCNR stage and a second MCNR stage. The first MCNR stage includes blending the current frame with either a cached image or a long-term reference image to obtain a fused image. The cached image is loaded from the buffer unit, and the long-term reference image is derived from the static region of each input frame in a sequence of input frames. The second MCNR stage includes blending the fused image with the other of the cached image or the long-term reference image to obtain an output image.

Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.

Abstract: An integrated circuit (IC) device includes a substrate with a power control circuit, front and back side metal layers, and first and second feed through vias (FTVs). The front side metal layer has first and second front side power rails. The back side metal layer has first and second back side power rails. The first FTV extends through the substrate, and couples the first front side power rail to the first back side power rail. The second FTV extends through the substrate, and couples the second front side power rail to the second back side power rail. The power control circuit is coupled to the first and second front side power rails, and is controllable to electrically connect the first front side power rail to the second front side power rail, or electrically disconnect the first front side power rail from the second front side power rail.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure comprises a first semiconductor device, a second semiconductor device, and a first semiconductor component. The first semiconductor device and the second semiconductor device defining a channel region. The first semiconductor component is disposed in the channel region and configured to control states of a plurality of components in the channel region. The first semiconductor device and the first semiconductor component are located adjacent to a boundary, and the first semiconductor component is electrically isolated from the first semiconductor device.

Abstract: A method and an image processing device for mura detection on a display are proposed. The method includes the following steps. An original image of the display is received and segmented into region of interest (ROI) patches. A predetermined range of spatial frequency components are filtered out from the ROI patches to generate filtered ROI patches. A mura defect is identified from the display according to the filtered ROI patches and predetermined mura patterns.

Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.

Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.

Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.

Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.

Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate. A method of forming a routing structure is also disclosed.

Abstract: A vertical-cavity surface emitting laser includes a substrate, a first reflector, an active region, an oxide layer, a second reflector, and a circular metal electrode. The first reflector is formed above the substrate. The active region is formed above the first reflector, and includes at least one quantum well. The at least one quantum well generates a laser beam with a plurality of modes. The oxide layer is formed above the active region and includes an oxide aperture. The second reflector is formed above the oxide layer. The circular metal electrode is formed in a circular concave in the second reflector. The circular metal electrode reflects other modes of the laser beam with the plurality of modes except for a fundamental mode and receive an operational voltage. A window exists between the circular concave and lets the laser beam with the fundamental mode pass.

Abstract: A method for performing one or more tasks, wherein each of the one or more tasks includes predicting behavior of one or more agents in an environment, the method comprising: obtaining a three-dimensional (3D) input tensor representing behaviors of the one or more agents in the environment across a plurality of time steps; generating an encoded representation of the 3D input tensor by processing the 3D input tensor using an encoder neural network, wherein 3D input tensor comprises a plurality of observed cells and a plurality of masked cells; and processing the encoded representation of the 3D input tensor using a decoder neural network to generate a 4D output tensor.

Abstract: A method and an image processing device for mura detection on a display are proposed. The method includes the following steps. An original image of the display is received and segmented into region of interest (ROI) patches. A predetermined range of spatial frequency components are filtered out from the ROI patches to generate filtered ROI patches. A mura defect is identified from the display according to the filtered ROI patches and predetermined mura patterns.

Abstract: A vertical-cavity surface emitting laser includes a substrate, a first reflector, an active region, an oxide layer, a second reflector, and a circular metal electrode. The first reflector is formed above the substrate. The active region is formed above the first reflector, and includes at least one quantum well. The at least one quantum well generates a laser beam with a plurality of modes. The oxide layer is formed above the active region and includes an oxide aperture. The second reflector is formed above the oxide layer. The circular metal electrode is formed in a circular concave in the second reflector. The circular metal electrode reflects other modes of the laser beam with the plurality of modes except for a fundamental mode and receive an operational voltage. A window exists between the circular concave and lets the laser beam with the fundamental mode pass.

Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate. A method of forming a routing structure is also disclosed.