Patents by Inventor Hao-Tien KAN
Hao-Tien KAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11929331Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.Type: GrantFiled: December 19, 2022Date of Patent: March 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang, Chung-Hsing Wang
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Publication number: 20230420369Abstract: An integrated circuit (IC) device includes a substrate with a power control circuit, front and back side metal layers, and first and second feed through vias (FTVs). The front side metal layer has first and second front side power rails. The back side metal layer has first and second back side power rails. The first FTV extends through the substrate, and couples the first front side power rail to the first back side power rail. The second FTV extends through the substrate, and couples the second front side power rail to the second back side power rail. The power control circuit is coupled to the first and second front side power rails, and is controllable to electrically connect the first front side power rail to the second front side power rail, or electrically disconnect the first front side power rail from the second front side power rail.Type: ApplicationFiled: September 2, 2022Publication date: December 28, 2023Inventors: Chin-Shen LIN, Luk LU, Hao-Tien KAN, Ren-Zheng LIAO
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Publication number: 20230260984Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure comprises a first semiconductor device, a second semiconductor device, and a first semiconductor component. The first semiconductor device and the second semiconductor device defining a channel region. The first semiconductor component is disposed in the channel region and configured to control states of a plurality of components in the channel region. The first semiconductor device and the first semiconductor component are located adjacent to a boundary, and the first semiconductor component is electrically isolated from the first semiconductor device.Type: ApplicationFiled: February 15, 2022Publication date: August 17, 2023Inventors: HAO-TIEN KAN, YAN-SHEN YOU, CHIN-SHEN LIN, KUO-NAN YANG, CHUNG-HSING WANG
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Publication number: 20230154849Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.Type: ApplicationFiled: January 18, 2023Publication date: May 18, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Yu LO, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG, Meng-Xiang LEE, Hao-Tien KAN, Jhih-Hong YE
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Publication number: 20230121445Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a boundary and a first conductive trace configured to be coupled to a first conductive pad disposed within the boundary of the substrate. The first conductive trace is inclined with respect to the boundary of the substrate.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Inventors: CHIN-SHEN LIN, WAN-YU LO, MENG-XIANG LEE, HAO-TIEN KAN, KUO-NAN YANG, CHUNG-HSING WANG
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Patent number: 11600568Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.Type: GrantFiled: June 18, 2021Date of Patent: March 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Yu Lo, Chung-Hsing Wang, Chin-Shen Lin, Kuo-Nan Yang, Meng-Xiang Lee, Hao-Tien Kan, Jhih-Hong Ye
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Publication number: 20220406716Abstract: Various layouts for conductive interconnects in the conductor layers in an integrated circuit are disclosed. Some or all of the conductive interconnects are included in a power delivery system. In general, the conductive interconnects in a first conductor layer are arranged according to an orthogonal layout and the conductive interconnects in a second conductor layer are arranged according to a non-orthogonal layout. Conductive stripes in a transition conductor layer positioned between the first and the second conductor layers electrically connect the conductive interconnects in the first conductor layer to the conductive interconnects in the second conductor layer.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wan-Yu LO, Chung-Hsing WANG, Chin-Shen LIN, Kuo-Nan YANG, Meng-Xiang LEE, Hao-Tien KAN, Jhih-Hong YE
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Patent number: 11532562Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate. A method of forming a routing structure is also disclosed.Type: GrantFiled: June 24, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Shen Lin, Wan-Yu Lo, Meng-Xiang Lee, Hao-Tien Kan, Kuo-Nan Yang, Chung-Hsing Wang
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Publication number: 20210407913Abstract: The present disclosure provides a routing structure. The routing structure includes a substrate having a first circuit region and a boundary surrounding the first circuit region. The routing structure also includes a first conductive trace coupled to a first conductive pad disposed in the first circuit region. The first conductive trace is inclined with respect to the boundary of the substrate. A method of forming a routing structure is also disclosed.Type: ApplicationFiled: June 24, 2020Publication date: December 30, 2021Inventors: CHIN-SHEN LIN, WAN-YU LO, MENG-XIANG LEE, HAO-TIEN KAN, KUO-NAN YANG, CHUNG-HSING WANG
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Patent number: 10467375Abstract: A method includes providing a symbolic power distribution network (PDN) map for a PDN of an circuit design including at least a first mesh that includes a plurality of map nodes; modeling at least one parasitic component that is provided on a branch of the symbolic PDN map and a pair of current sources that are provided at two respective map nodes of the symbolic PDN map; providing a matrix equation based on an interrelated conduction behavior among the parasitic component and the pair of current sources, wherein the matrix equation includes a current source term representing the pair of current sources and an unknown variable term representing a voltage level of at least a map node of the symbolic PDN map; and based on the matrix equation, expanding the unknown variable term in a frequency-domain as a sum of plural mathematical components while keeping the current source term intact.Type: GrantFiled: September 6, 2017Date of Patent: November 5, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hui Yu Lee, Hao-Tien Kan
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Patent number: 10268788Abstract: A method includes building a driver model in frequency domain, extracting S (scattering) parameters, the S parameters to describe a real curve that represents a real signal channel between the driver model and a load circuit, and generating, based on the extracted S parameters, an approaching curve of the real curve, the approaching curve being expressed in an approaching equation.Type: GrantFiled: May 19, 2017Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hui-Yu Lee, Hao-Tien Kan
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Publication number: 20180336305Abstract: A method includes building a driver model in frequency domain, extracting S (scattering) parameters, the S parameters to describe a real curve that represents a real signal channel between the driver model and a load circuit, and generating, based on the extracted S parameters, an approaching curve of the real curve, the approaching curve being expressed in an approaching equation.Type: ApplicationFiled: May 19, 2017Publication date: November 22, 2018Inventors: HUI-YU LEE, HAO-TIEN KAN
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Publication number: 20180165407Abstract: A method includes providing a symbolic power distribution network (PDN) map for a PDN of an circuit design including at least a first mesh that includes a plurality of map nodes; modeling at least one parasitic component that is provided on a branch of the symbolic PDN map and a pair of current sources that are provided at two respective map nodes of the symbolic PDN map; providing a matrix equation based on an interrelated conduction behavior among the parasitic component and the pair of current sources, wherein the matrix equation includes a current source term representing the pair of current sources and an unknown variable term representing a voltage level of at least a map node of the symbolic PDN map; and based on the matrix equation, expanding the unknown variable term in a frequency-domain as a sum of plural mathematical components while keeping the current source term intact.Type: ApplicationFiled: September 6, 2017Publication date: June 14, 2018Inventors: Hui Yu LEE, Hao-Tien KAN