Patents by Inventor Hao-Wei Lin
Hao-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240147646Abstract: A portable data accessing device and more particularly the use of multi-port interfaces on a data accessing device disclosed. The multi-port data accessing device includes an inner body, one or a plurality of moving-caps, one or a plurality of grips, a pump-action and one or a plurality of locking/releasing mechanisms.Type: ApplicationFiled: January 5, 2024Publication date: May 2, 2024Inventors: Yi-Ting Lin, Hsien-Chih Chang, Chang-Hsing Lin, Hao-Yin Lo, Ben Wei Chen
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Publication number: 20240144426Abstract: A super resolution (SR) image generation circuit includes an image scale-up circuit, a stable SR processing circuit, a generative adversarial network (GAN) processing circuit, and a configurable basic block pool circuit. The image scale-up circuit is arranged to receive and process an input image to generate a scaled-up image. The stable SR processing circuit is arranged to receive a feature map of the input image to generate a stable delta value. The GAN processing circuit is arranged to receive the feature map to generate a GAN delta value. The configurable basic block pool circuit is arranged to dynamically configure a plurality of basic blocks according to a depth requirement of the input image, to generate a configuration result. The SR image generation circuit generates an SR image according to the scaled-up image, the stable delta value, and the GAN delta value.Type: ApplicationFiled: April 20, 2023Publication date: May 2, 2024Applicant: Realtek Semiconductor Corp.Inventors: Shang-Yen Lin, Yi-Ting Bao, HAO-RAN WANG, Chia-Wei Yu
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Patent number: 11966352Abstract: An information handling system with modular riser components for receiving expansion cards having various requirements. The system includes a riser body assembly having a common support structure for receiving expansion cards. The common support structure may be coupled to different expansion structures to provide support of expansion cards having requirements that would not be met by the common support structure alone.Type: GrantFiled: October 8, 2020Date of Patent: April 23, 2024Assignee: Dell Products L.P.Inventors: Yu-Feng Lin, Hao-Cheng Ku, Yi-Wei Lu
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Patent number: 11963295Abstract: Provided are a circuit apparatus, a manufacturing method thereof, and a circuit system. The circuit apparatus includes a flexible circuit board, a flexible packaging material layer and an electronic device. The flexible circuit board has at least one hollow pattern, wherein the flexible circuit board has an inner region and a peripheral region surrounding the inner region, and has a first surface and a second surface opposite to each other. The flexible packaging material layer is disposed in the at least one hollow pattern. The electronic device is disposed on the first surface of the flexible circuit board and electrically connected with the flexible circuit board.Type: GrantFiled: January 27, 2022Date of Patent: April 16, 2024Assignee: Industrial Technology Research InstituteInventors: Hung-Hsien Ko, Yi-Cheng Lu, Heng-Yin Chen, Hao-Wei Yu, Te-Hsun Lin
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Patent number: 11935804Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.Type: GrantFiled: April 10, 2023Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
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Publication number: 20240069618Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.Type: ApplicationFiled: April 27, 2023Publication date: February 29, 2024Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
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Publication number: 20240071999Abstract: A first polymer layer is formed across a package region and a test region. A first metal pattern is formed in the package region and a first test pattern is simultaneously formed in the test region. The first metal pattern has an upper portion located on the first polymer layer and a lower portion penetrating through the first polymer layer, and the first test pattern is located on the first polymer layer and has a first opening exposing the first polymer layer. A second polymer layer is formed on the first metal pattern in the package region and a second test pattern is simultaneously formed on the first test pattern in the test region. The second polymer layer has a second opening exposing the upper portion of the first metal pattern, and the second test pattern has a third opening greater than the first opening of the first test pattern.Type: ApplicationFiled: August 24, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tseng Hsing Lin, Chien-Hsun Lee, Tsung-Ding Wang, Jung-Wei Cheng, Hao-Cheng Hou, Sheng-Chi Lin, Jeng-An Wang, Yao-Cheng Wu
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Publication number: 20240071981Abstract: A method of fabricating a semiconductor structure includes the following steps. A semiconductor wafer is provided. A plurality of first surface mount components and a plurality of second surface mount components are bonded onto the semiconductor wafer, wherein a first portion of each of the second surface mount components is overhanging a periphery of the semiconductor wafer. A first barrier structure is formed in between the second surface mount components and the semiconductor wafer. An underfill structure is formed under a second portion of each of the second surface mount components, wherein the first barrier structure blocks the spreading of the underfill structure from the second portion to the first portion.Type: ApplicationFiled: November 1, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
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Publication number: 20110154698Abstract: A multimedia greeting card in accordance with the present invention has a base, a control circuit board, a screen, a speaker and a cover. The control circuit board and the speaker are mounted in the base, and the screen is mounted on the base. The screen and the speaker are electrically connected to the control circuit board. The cover is pivotally mounted on the base. People can record audio-visual information and store data in a storage unit of the control circuit board. When the multimedia greeting card is actuated, the multimedia information is presented by the screen and speaker.Type: ApplicationFiled: December 28, 2009Publication date: June 30, 2011Inventor: Hao-Wei Lin
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Patent number: 6336931Abstract: An automatic bone drilling apparatus for surgery operation uses a computer to control a hand tool drilling device to drill opening in skeleton. The computer has a fuzzy logic software to control the hand tool operation through a control box and a manual-automatic mode switch box. The hand tool drilling device may be securely mounted on the patient. Drilling location and size and depth may be precisely controlled to enhance surgical operation safety. It is particularly useful for drilling patient skeleton for brain surgery operation.Type: GrantFiled: May 17, 2000Date of Patent: January 8, 2002Inventors: Yeh-Liang Hsu, Shih-Tseng Lee, Chong-Fai Wang, Jia-Wen Chen, Hao-Wei Lin, Tsung-Cheng Huang