Abstract: An embodiment of the invention provides a data authentication device. The data authentication device may include a main memory, a backup memory, a platform control hub (PCH) and an embedded controller (EC). The main memory may be configured to store data. The backup memory may be configured to back up the data stored in the main memory. The PCH is coupled to the main memory and generates a write command to write a first data image to the main memory, wherein the first data image comprises updated data and a digital signature. The EC is coupled to the main memory, the backup memory and the PCH and obtains the first data image from the PCH. When the EC detects a write command, the EC may perform an authentication for the updated data based on the first data image or a second data image corresponding to the first data image.

Abstract: A chip having a debug memory interface includes a processing unit, an internal storage unit, a debug memory interface, and a detection unit. The internal storage unit is used to record status data during operation of the processing unit. The detection unit is used to detect whether the debug memory interface is electrically connected to an external memory device. When the debug memory interface is judged to be electrically connected to the external memory device, a control signal is transmitted to the processing unit in order to trigger the processing unit to read a debug program from the external memory device and execute the debug program to run a debug mode based on the status data.

Abstract: A bus system is provided. A plurality of slave devices are electrically connected to a master device through an enhanced serial peripheral interface (eSPI) bus. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. In a first phase of a plurality of phases in each assignment period of an assignment stage after a synchronization stage, the first slave device is configured to control the alert handshake control line to a second voltage level via the alert handshake pin. In the phases of each of the assignment periods except for the first phase, a first slave device of the slave devices is configured to control the alert handshake control line to communicate with the slave devices via the alert handshake pin. The first phase corresponds to a first slave device.

Abstract: A bus system is provided. A plurality of slave devices are electrically connected to a master device through an enhanced serial peripheral interface (eSPI) bus. The slave devices are electrically connected together via a control line. A first slave device is configured to provide a first clock signal to each second slave device via the control line, so that a second clock signal of each second slave device is synchronized with the first clock signal. After the second clock signals are synchronized with the first clock signal, each second slave device is configured to adjust a phase of the second clock signal in a clock phase shift stage, so that each second clock signal has a phase difference with the first clock signal. The phase differences between the second clock signals of the second slave devices and the first clock signal are different.

Abstract: A bus system is provided. The bus system includes a master device, an enhanced serial peripheral interface (eSPI) bus, an SPI bus, a memory device electrically connected to the master device via the SPI bus, and a plurality of slave devices electrically connected to the master device via the eSPI bus. Each of the slave devices has a pin, and the pins of the slave devices are electrically connected together via a control line. After obtaining program code from the memory device via the master device, a first slave device is configured to decrypt the program code according to a first security code, and transmit the program code decrypted by the first security code to the slave devices via the control line, so that the program code decrypted by the first security code is decrypted in the slave devices according to a decryption sequence.

Abstract: A bus system is provided. A plurality of slave devices are electrically connected to a master device through an enhanced serial peripheral interface (eSPI) bus. The slave devices are electrically connected together via a control line. A first slave device is configured to provide a first clock signal to each second slave device via the control line, so that a second clock signal of each second slave device is synchronized with the first clock signal. After the second clock signals are synchronized with the first clock signal, each second slave device is configured to adjust a phase of the second clock signal in a clock phase shift stage, so that each second clock signal has a phase difference with the first clock signal. The phase differences between the second clock signals of the second slave devices and the first clock signal are different.

Abstract: A cascade extension device and a cascade system having the cascade extension device are provided. The cascade extension device includes a control module, a buffer module, a storage module, and a selecting output module. The cascade system includes a processor and a plurality of extension devices. The processor may simultaneously control the plurality of extension devices through judging the data packet received as a write command, a read command, or a bypass command by a plurality of extension devices.

Abstract: A bus system is provided. A memory device is electrically connected to a master device via a serial peripheral interface (SPI) bus. A plurality of slave devices are electrically connected to the master device via an enhanced SPI (eSPI) bus. Each of the slave devices has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert-handshake control line. The first slave device is electrically connected to the memory device via the SPI bus. After obtaining a program code from the memory device, the first slave device verifies the program code using a security code and controls the alert-handshake control line to unlock all the slave devices except for the first slave device via the alert handshake pin in response to the program code being verified. The unlocked slave devices communicate with the master device via the eSPI bus.

Abstract: A bus system is provided. The bus system includes a master device, an enhanced serial peripheral interface (eSPI) bus, an SPI bus, a memory device electrically connected to the master device via the SPI bus, and a plurality of slave devices electrically connected to the master device via the eSPI bus. Each of the slave devices has a pin, and the pins of the slave devices are electrically connected together via a control line. After obtaining program code from the memory device via the master device, a first slave device is configured to decrypt the program code according to a first security code, and transmit the program code decrypted by the first security code to the slave devices via the control line, so that the program code decrypted by the first security code is decrypted in the slave devices according to a decryption sequence.

Abstract: A bus system is provided. A memory device is electrically connected to a master device via a serial peripheral interface (SPI) bus. A plurality of slave devices are electrically connected to the master device via an enhanced SPI (eSPI) bus. Each of the slave devices has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert-handshake control line. The first slave device is electrically connected to the memory device via the SPI bus. After obtaining a program code from the memory device, the first slave device verifies the program code using a security code and controls the alert-handshake control line to unlock all the slave devices except for the first slave device via the alert handshake pin in response to the program code being verified. The unlocked slave devices communicate with the master device via the eSPI bus.

Abstract: A bus system is provided. A plurality of slave devices are electrically connected to a master device through an enhanced serial peripheral interface (eSPI) bus. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. In a first phase of a plurality of phases in each assignment period of an assignment stage after a synchronization stage, the first slave device is configured to control the alert handshake control line to a second voltage level via the alert handshake pin. In the phases of each of the assignment periods except for the first phase, a first slave device of the slave devices is configured to control the alert handshake control line to communicate with the slave devices via the alert handshake pin. The first phase corresponds to a first slave device.

Abstract: An integrated circuit includes a specific pin, an output circuit, a voltage detector, and a controller. The output circuit is coupled to the specific pin. The voltage detector obtains a detection voltage value from the specific pin. In response to an alert request, the controller provides a control signal to the output circuit based on the detection voltage value, so as to selectively control the output circuit to transmit the alert signal to the specific pin. When the control signal instructs the integrated circuit to operate in a blocking mode, the output circuit blocks the alert signal from being transmitted to the specific pin. When the control signal instructs the integrated circuit to operate in a transmission mode, the output circuit transmits the alert signal to the specific pin.

Abstract: A bus system is provided. The bus system includes a master device and a plurality of slave devices electrically connected to the master device. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. When the alert handshake control line is at a first voltage level and a first slave device want to communicate with the master device, the first slave device controls the alert handshake control line to a second voltage level via the alert handshake pin, such that the slave devices enter a synchronization stage. Among phases of each assignment period, in a first phase corresponding to the first slave device, the first slave device controls the alert handshake control line to the second voltage level via the alert handshake pin.

Abstract: A cascade extension device and a cascade system having the cascade extension device are provided. The cascade extension device includes a control module, a buffer module, a storage module, and a selecting output module. The cascade system includes a processor and a plurality of extension devices. The processor may simultaneously control the plurality of extension devices through judging the data packet received as a write command, a read command, or a bypass command by a plurality of extension devices.

Abstract: A chip having a debug memory interface includes a processing unit, an internal storage unit, a debug memory interface, and a detection unit. The internal storage unit is used to record status data during operation of the processing unit. The detection unit is used to detect whether the debug memory interface is electrically connected to an external memory device. When the debug memory interface is judged to be electrically connected to the external memory device, a control signal is transmitted to the processing unit in order to trigger the processing unit to read a debug program from the external memory device and execute the debug program to run a debug mode based on the status data.

Abstract: An integrated circuit includes a specific pin, an output circuit, a voltage detector, and a controller. The output circuit is coupled to the specific pin. The voltage detector obtains a detection voltage value from the specific pin. In response to an alert request, the controller provides a control signal to the output circuit based on the detection voltage value, so as to selectively control the output circuit to transmit the alert signal to the specific pin. When the control signal instructs the integrated circuit to operate in a blocking mode, the output circuit blocks the alert signal from being transmitted to the specific pin. When the control signal instructs the integrated circuit to operate in a transmission mode, the output circuit transmits the alert signal to the specific pin.

Abstract: A bus system is provided. The bus system includes a master device, a bus, and a plurality of slave devices electrically connected to the master device via the bus. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert-handshake control line. When a first slave device communicates with the master device through the bus, in a first phase of a plurality of phases in each assignment period, the first slave device sets the alert-handshake control line to a first voltage level via the alert handshake pin, wherein the first phase corresponds to the first slave device. In the phases other than the first phase in each assignment period, the alert-handshake control line is at a second voltage level. Each of the phases includes two clock cycles.

Abstract: A bus system is provided. The bus system includes a master device, an enhanced serial peripheral interface (eSPI) bus, a plurality of slave devices electrically connected to the master device via the eSPI bus, and a first resistor. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. The first resistor is coupled between the alert handshake control line and a power supply. Each slave device obtains the number of slave devices according to a first voltage of the alert handshake control line.

Abstract: A bus system is provided. The bus system includes a master device and a plurality of slave devices electrically connected to the master device. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. When the alert handshake control line is at a first voltage level and a first slave device want to communicate with the master device, the first slave device controls the alert handshake control line to a second voltage level via the alert handshake pin, such that the slave devices enter a synchronization stage. Among phases of each assignment period, in a first phase corresponding to the first slave device, the first slave device controls the alert handshake control line to the second voltage level via the alert handshake pin.