Patents by Inventor Hao-Yi Tsai

Hao-Yi Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210057302
    Abstract: In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.
    Type: Application
    Filed: November 9, 2020
    Publication date: February 25, 2021
    Inventors: Tsung-Hsien Chiang, Yu-Chih Huang, Ting-Ting Kuo, Chih-Hsuan Tai, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai, Chiahung Liu, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20210057144
    Abstract: A structure includes an encapsulating material, and a coil including a through-conductor. The through-conductor is in the encapsulating material, with a top surface of the through-conductor coplanar with a top surface of the encapsulating material, and a bottom surface of the through-conductor coplanar with a bottom surface of the encapsulating material. A metal plate is underlying the encapsulating material. A slot is in the metal plate and filled with a dielectric material. The slot has a portion overlapped by the coil.
    Type: Application
    Filed: November 9, 2020
    Publication date: February 25, 2021
    Inventors: Chuei-Tang Wang, Wei-Ting Chen, Chieh-Yen Chen, Hao-Yi Tsai, Ming Hung Tseng, Hung-Yi Kuo, Chen-Hua Yu
  • Publication number: 20210047810
    Abstract: A portable drinking water generator includes a micro gas pump, a micro condenser module, and a micro liquid pump. The portable drinking water generator utilizes the micro gas pump to draw air and transmit the purified air to the micro condenser module. The water in the air is condensed into liquid water by the micro condenser module. Afterwards, the liquid water is collected and transported to a water purification module by the micro liquid pump. The liquid water is filtered by the water purification module and becomes drinkable drinking water. Therefore, the portable drinking water generator can achieve generating drinking water.
    Type: Application
    Filed: July 20, 2020
    Publication date: February 18, 2021
    Inventors: Hao-Jan Mou, Ching-Sung Lin, Yung-Lung Han, Chi-Feng Huang, Chun-Yi Kuo, Chang-Yen Tsai, Wei-Ming Lee
  • Publication number: 20210020538
    Abstract: A package structure includes a semiconductor die, a redistribution circuit structure, and a metallization element. The semiconductor die has an active side and an opposite side opposite to the active side. The redistribution circuit structure is disposed on the active side and is electrically coupled to the semiconductor die. The metallization element has a plate portion and a branch portion connecting to the plate portion, wherein the metallization element is electrically isolated to the semiconductor die, and the plate portion of the metallization element is in contact with the opposite side.
    Type: Application
    Filed: July 18, 2019
    Publication date: January 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Chen, Hao-Yi Tsai, Kuo-Lung Pan, Tin-Hao Kuo, Po-Yuan Teng, Chi-Hui Lai
  • Publication number: 20210013177
    Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Publication number: 20210005586
    Abstract: A semiconductor structure includes a semiconductor package and a connector. The semiconductor package includes a die and a redistribution structure. The redistribution structure is disposed over the die, and includes a plurality of conductive patterns stacking on one another and electrically connected to the die. The connector is disposed on the redistribution structure, and includes a connecting element. The connecting element penetrates the conductive patterns and is electrically connected to the die.
    Type: Application
    Filed: September 17, 2020
    Publication date: January 7, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Hui Lai, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Tin-Hao Kuo
  • Publication number: 20210005554
    Abstract: In an embodiment, a device includes: a back-side redistribution structure including: a metallization pattern on a first dielectric layer; and a second dielectric layer on the metallization pattern; a through via extending through the first dielectric layer to contact the metallization pattern; an integrated circuit die adjacent the through via on the first dielectric layer; a molding compound on the first dielectric layer, the molding compound encapsulating the through via and the integrated circuit die; a conductive connector extending through the second dielectric layer to contact the metallization pattern, the conductive connector being electrically connected to the through via; and an intermetallic compound at the interface of the conductive connector and the metallization pattern, the intermetallic compound extending only partially into the metallization pattern.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Tzu-Sung Huang, Hsiu-Jen Lin, Hao-Yi Tsai, Ming Hung Tseng, Tsung-Hsien Chiang, Tin-Hao Kuo, Yen-Liang Lin
  • Publication number: 20200410198
    Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ying-Cheng Tseng
  • Publication number: 20200411439
    Abstract: A semiconductor device includes a first chip package, a heat dissipation structure and an adapter. The first chip package includes a semiconductor die laterally encapsulated by an insulating encapsulant, the semiconductor die has an active surface and a back surface opposite to the active surface. The heat dissipation structure is connected to the chip package. The adapter is disposed over the first chip package and electrically connected to the semiconductor die.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yuan Teng, Hung-Yi Kuo, Hao-Yi Tsai, Tin-Hao Kuo, Yu-Chia Lai, Shih-Wei Chen
  • Patent number: 10879221
    Abstract: A package-on-package structure includes a first package, a second package and first intermetallic features. The first package includes at least one semiconductor die, an insulating encapsulant, a redistribution layer and conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant. The conductive pads are located at a surface of the insulating encapsulant. The second package is stacked on the first package and electrically connected to the conductive pads through connectors. The first intermetallic features are sandwiched in between the conductive pads and the connectors and have a control region and a growth region. The connectors are connected to the control region, and the growth region spreads out from a periphery of the control region such that the spreading of the growth region extends away from the conductive pads in a direction towards the semiconductor die.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ti Lu, Chih-Hua Chen, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin
  • Patent number: 10878073
    Abstract: A device package includes a sensor die, one or more additional dies adjacent the sensor die, and a molding compound encircling the sensor die and the one or more additional dies. The device package further includes redistribution layers over the sensor die, the one or more additional dies, and the molding compound. The redistribution layers include first conductive features in a first dielectric layer. The first conductive features electrically connect the sensor die to the one or more additional dies. The redistribution layers further include an array of electrodes in a second dielectric layer over the first dielectric layer and electrically connected to the sensor die.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chih-Hsuan Tai, Yu-Jen Cheng, Chih-Hua Chen, Yu-Feng Chen, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20200402927
    Abstract: A manufacturing method of a semiconductor package includes at least the following steps. A rear surface of a semiconductor die is attached to a patterned dielectric layer of a first redistribution structure through a die attach material, where a thickness of a portion of the die attach material filling a gap between the rear surface of the semiconductor die and a recessed area of the patterned dielectric layer is greater than a thickness of another portion of the die attach material interposed between the rear surface of the semiconductor die and a non-recessed area of the patterned dielectric layer. An insulating encapsulant is formed on the patterned dielectric layer of the first redistribution structure to cover the semiconductor die and the die attach material. Other methods for forming a semiconductor package are also provided.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Hao-Yi Tsai, Tin-Hao Kuo, Ching-Yao Lin, Teng-Yuan Lo, Chih Wang
  • Patent number: 10867911
    Abstract: A method includes forming a coil over a carrier, encapsulating the coil in an encapsulating material, planarizing a top surface of the encapsulating material until the coil is exposed, forming at least one dielectric layer over the encapsulating material and the coil, and forming a plurality of redistribution lines extending into the at least one dielectric layer. The plurality of redistribution lines is electrically coupled to the coil.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tsung-Hsien Chiang, Hao-Yi Tsai, Hung-Yi Kuo, Ming Hung Tseng
  • Publication number: 20200388584
    Abstract: A semiconductor structure includes a transceiver, a molding surrounding the transceiver, and a RDL disposed over the transceiver. The RDL includes an antenna and a dielectric layer. The antenna is disposed over and electrically connected to the transceiver. The dielectric layer surrounds the antenna. The antenna includes an elongated portion and a via portion. The elongated portion extends over the molding, and the via portion is electrically connected to the transceiver.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 10, 2020
    Inventors: VINCENT CHEN, HUNG-YI KUO, CHUEI-TANG WANG, HAO-YI TSAI, CHEN-HUA YU, WEI-TING CHEN, MING HUNG TSENG, YEN-LIANG LIN
  • Patent number: 10861841
    Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Cheng Tseng, Yu-Chih Huang, Chih-Hsuan Tai, Ting-Ting Kuo, Chi-Hui Lai, Ban-Li Wu, Chiahung Liu, Hao-Yi Tsai
  • Publication number: 20200381362
    Abstract: A semiconductor package includes a first wafer, a second wafer, and an interconnect. The first wafer includes a first die, a first encapsulating material encapsulating the first die, and a first redistribution structure disposed over the first die and the first encapsulating material. The second wafer includes a second die, a second encapsulating material encapsulating the second die, and a second redistribution structure disposed over the second die and the second encapsulating material, wherein the second redistribution structure faces the first redistribution structure. The interconnect is disposed between the first wafer and the second wafer and electrically connecting the first redistribution structure and the second redistribution structure, wherein the interconnect includes a substrate and a plurality of through vias extending through the substrate for connecting the first redistribution structure and the second redistribution structure.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 3, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Cheng Tseng, Hao-Yi Tsai, Tin-Hao Kuo, Chia-Hung Liu, Chi-Hui Lai
  • Publication number: 20200381325
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Patent number: 10853616
    Abstract: A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yu-Feng Chen, Chih-Hua Chen, Hao-Yi Tsai, Chung-Shi Liu
  • Patent number: 10847304
    Abstract: A structure includes an encapsulating material, and a coil including a through-conductor. The through-conductor is in the encapsulating material, with a top surface of the through-conductor coplanar with a top surface of the encapsulating material, and a bottom surface of the through-conductor coplanar with a bottom surface of the encapsulating material. A metal plate is underlying the encapsulating material. A slot is in the metal plate and filled with a dielectric material. The slot has a portion overlapped by the coil.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Wei-Ting Chen, Chieh-Yen Chen, Hao-Yi Tsai, Ming Hung Tseng, Hung-Yi Kuo, Chen-Hua Yu
  • Publication number: 20200365569
    Abstract: A package-on-package structure includes a first package, a second package and first intermetallic features. The first package includes at least one semiconductor die, an insulating encapsulant, a redistribution layer and conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant. The conductive pads are located at a surface of the insulating encapsulant. The second package is stacked on the first package and electrically connected to the conductive pads through connectors. The first intermetallic features are sandwiched in between the conductive pads and the connectors and have a control region and a growth region. The connectors are connected to the control region, and the growth region spreads out from a periphery of the control region such that the spreading of the growth region extends away from the conductive pads in a direction towards the semiconductor die.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Ti Lu, Chih-Hua Chen, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin