Patents by Inventor Hao-Yi Tsai

Hao-Yi Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11664315
    Abstract: A structure including a first die, a second die, a first insulating encapsulant, an interconnection die, and a second insulating encapsulant is provided. The first die includes a first bonding structure. The first bonding structure includes a first dielectric layer and a first conductive pad embedded in the first dielectric layer. The second die includes a second bonding structure. The second bonding structure includes a second dielectric layer and a second conductive pad embedded in the second dielectric layer. The first insulating encapsulant laterally encapsulates the first die and the second die. The interconnection die includes a third bonding structure. The third bonding structure includes a third dielectric layer and third conductive pads embedded in the third dielectric layer. The second insulating encapsulant laterally encapsulates the interconnection die. The third bonding structure is in contact with the first bonding structure and the second bonding structure.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: May 30, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hao-Yi Tsai, Tzuan-Horng Liu, Ting Hao Kuo
  • Patent number: 11664325
    Abstract: A package structure including a first semiconductor die, a second semiconductor die, first conductive pillars and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure and a first redistribution circuit structure. The semiconductor substrate includes a first portion and a second portion disposed on the first portion. The interconnect structure is disposed on the second portion, the first redistribution circuit structure is disposed on the interconnect structure, and the lateral dimension of the first portion is greater than the lateral dimension of the second portion. The second semiconductor die is disposed on the first semiconductor die. The first conductive pillars are disposed on the first redistribution circuit structure of the first semiconductor die. The first insulating encapsulation is disposed on the first portion.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: May 30, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Cheng-Chieh Hsieh, Hsiu-Jen Lin, Hui-Jung Tsai, Hung-Yi Kuo, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin, Chun-Ti Lu, Chung-Ming Weng
  • Publication number: 20230154764
    Abstract: A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.
    Type: Application
    Filed: March 21, 2022
    Publication date: May 18, 2023
    Inventors: Tzu-Sung Huang, Tsung-Hsien Chiang, Ming Hung Tseng, Hao-Yi Tsai, Yu-Hsiang Hu, Chih-Wei Lin, Lipu Kris Chuang, Wei Lun Tsai, Kai-Ming Chiang, Ching Yao Lin, Chao-Wei Li, Ching-Hua Hsieh
  • Publication number: 20230152542
    Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.
    Type: Application
    Filed: January 3, 2022
    Publication date: May 18, 2023
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
  • Patent number: 11646296
    Abstract: A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo-Lung Pan, Ting Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
  • Patent number: 11646255
    Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo Lung Pan, Yu-Chia Lai, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu, Po-Yuan Teng, Teng-Yuan Lo, Mao-Yen Chang
  • Patent number: 11640935
    Abstract: A semiconductor package includes a redistribution structure, a supporting layer, a semiconductor device, and a transition waveguide structure. The redistribution structure includes a plurality of connectors. The supporting layer is formed over the redistribution structure and disposed beside and between the plurality of connectors. The semiconductor device is disposed on the supporting layer and bonded to the plurality of connectors, wherein the semiconductor device includes a device waveguide. The transition waveguide structure is disposed on the supporting layer adjacent to the semiconductor device, wherein the transition waveguide structure is optically coupled to the device waveguide.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: May 2, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Hsiu-Jen Lin, Ming-Che Ho, Yu-Hsiang Hu, Chewn-Pu Jou, Cheng-Tse Tang
  • Publication number: 20230126259
    Abstract: A fingerprint sensor includes a die, a plurality of conductive structures, an encapsulant, a plurality of conductive patterns, a first dielectric layer, a second dielectric layer, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The conductive patterns are over the die and are electrically connected to the die and the conductive structures. Top surfaces of the conductive patterns are flat. The first dielectric layer is over the die and the encapsulant. A top surface of the first dielectric layer is coplanar with top surfaces of the conductive patterns. The second dielectric layer covers the first dielectric layer and the conductive patterns. The redistribution structure is over the rear surface of the die.
    Type: Application
    Filed: December 22, 2022
    Publication date: April 27, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ying-Cheng Tseng
  • Patent number: 11635566
    Abstract: An integrated circuit package and a method of forming the same are provided. The integrated circuit package includes a photonic integrated circuit die. The photonic integrated circuit die includes an optical coupler. The integrated circuit package further includes an encapsulant encapsulating the photonic integrated circuit die, a first redistribution structure over the photonic integrated circuit die and the encapsulant, and an opening extending through the first redistribution structure and exposing the optical coupler.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan Tai, Chung-Ming Weng, Hung-Yi Kuo, Cheng-Chieh Hsieh, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20230123427
    Abstract: A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Hao-Yi Tsai, Tin-Hao Kuo
  • Publication number: 20230120191
    Abstract: A semiconductor device, a circuit board structure and a manufacturing forming thereof are provided. A circuit board structure includes a core layer, a first build-up layer and a second build-up layer. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The circuit board structure has a plurality of stress releasing trenches extending into the first build-up layer and the second build-up layer.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Yu-Chia Lai, Po-Yuan Teng
  • Patent number: 11631658
    Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chih Huang, Chi-Hui Lai, Ban-Li Wu, Ying-Cheng Tseng, Ting-Ting Kuo, Chih-Hsuan Tai, Hao-Yi Tsai, Chuei-Tang Wang, Chung-Shi Liu, Chen-Hua Yu, Chiahung Liu
  • Publication number: 20230116861
    Abstract: Coil structures and methods of forming are provided. The coil structure includes a substrate. A plurality of coils is disposed over the substrate, each coil comprising a conductive element that forms a continuous spiral having a hexagonal shape in a plan view of the coil structure. The plurality of coils is arranged in a honeycomb pattern, and each conductive element is electrically connected to an external electrical circuit.
    Type: Application
    Filed: December 13, 2022
    Publication date: April 13, 2023
    Inventors: Tzu-Sung Huang, Chen-Hua Yu, Hao-Yi Tsai, Hung-Yi KUO, Ming Hung Tseng
  • Publication number: 20230114652
    Abstract: A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 13, 2023
    Inventors: Chen-Hua Yu, Kuo-Chung Yee, Hao-Yi Tsai, Tin-Hao Kuo
  • Publication number: 20230110420
    Abstract: A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 13, 2023
    Inventors: Ying-Cheng Tseng, Yu-Chih Huang, Chih-Hsuan Tai, Ting-Ting Kuo, Chi-Hui Lai, Ban-Li Wu, Chiahung Liu, Hao-Yi Tsai
  • Patent number: 11626339
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Patent number: 11625940
    Abstract: A fingerprint sensor package and method are provided. The fingerprint sensor package comprises a fingerprint sensor along with a fingerprint sensor surface material and electrical connections from a first side of the fingerprint sensor to a second side of the fingerprint sensor. A high voltage chip is connected to the fingerprint sensor and then the fingerprint sensor package with the high voltage chip are connected to a substrate, wherein the substrate has an opening to accommodate the presence of the high voltage chip.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Yu-Feng Chen, Chih-Hua Chen, Hao-Yi Tsai, Chung-Shi Liu
  • Publication number: 20230103560
    Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.
    Type: Application
    Filed: November 14, 2022
    Publication date: April 6, 2023
    Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
  • Patent number: 11614592
    Abstract: Photonic devices and methods of manufacture are provided. In embodiments a fill material and/or a secondary waveguide are utilized in order to protect other internal structures such as grating couplers from the rigors of subsequent processing steps. Through the use of these structures at the appropriate times during the manufacturing process, damage and debris that would otherwise interfere with the manufacturing process of the device or operation of the device can be avoided.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: March 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Chih-Hsuan Tai, Hua-Kuei Lin, Tsung-Yuan Yu, Min-Hsiang Hsu
  • Publication number: 20230090895
    Abstract: In an embodiment, a device includes: a first redistribution structure including a first dielectric layer; a die adhered to a first side of the first redistribution structure; an encapsulant laterally encapsulating the die, the encapsulant being bonded to the first dielectric layer with first covalent bonds; a through via extending through the encapsulant; and first conductive connectors electrically connected to a second side of the first redistribution structure, a subset of the first conductive connectors overlapping an interface of the encapsulant and the die.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 23, 2023
    Inventors: Kuo Lung Pan, Shu-Rong Chun, Teng-Yuan Lo, Hung-Yi Kuo, Chih-Horng Chang, Tin-Hao Kuo, Hao-Yi Tsai