Patents by Inventor Hao-Yin Tsai

Hao-Yin Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240104889
    Abstract: A system for detecting a proximate object includes one or more cameras and one or more illuminators. The proximate object is detected by obtaining image data captured by the one or more cameras, where the image data is captured when at least one of the one or more illuminators are illuminated, determining brightness statistics from the image data, and determining whether the brightness statistics satisfies a predetermined threshold. The proximate object is determined to be detected in accordance with a determination that the brightness statistics satisfies the predetermined threshold.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 28, 2024
    Inventors: Alper Yildirim, Chia-Yin Tsai, Hao Qin, Hua Gao, Tom Sengelaub, Martin Subert, Petr Bour
  • Patent number: 7973310
    Abstract: Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: July 5, 2011
    Assignee: Chipmos Technologies Inc.
    Inventors: David Wei Wang, An-Hong Liu, Hao-Yin Tsai, Hsiang-Ming Huang, Yi-Chang Lee, Shu-Ching Ho
  • Publication number: 20100007001
    Abstract: Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.
    Type: Application
    Filed: July 10, 2009
    Publication date: January 14, 2010
    Inventors: David Wei Wang, An-Hong Liu, Hao-Yin Tsai, Hsiang-Ming Huang, Yi-Chang Lee, Shu-Ching Ho
  • Publication number: 20090283905
    Abstract: A conductive structure of a chip is provided. The conductive structure comprises a ground layer, a dielectric layer, a redistribution layer, an under bump metal and a solder bump. The ground layer electrically connects to the ground pad of the chip, while the dielectric layer overlays the ground layer. Thus, the conductive layer can result in impedance matching, and the packaged chip is adapted to transmit a high frequency signal.
    Type: Application
    Filed: October 31, 2008
    Publication date: November 19, 2009
    Inventors: Hsiang-Ming HUANG, An-Hong Liu, Yi-Chang Lee, Hao-Yin Tsai, Shu-Ching Ho
  • Publication number: 20090236741
    Abstract: A conductive structure of a chip and a method for manufacturing the conductive structure are provided. An under bump metal (UBM) is formed on the redistribution layer (RDL) by performing an electroless plating process. Subsequently, the solder bump is formed on the under bump metal for electrical connection. Thus, the photomask can be economized and the cost of manufacturing can be reduced.
    Type: Application
    Filed: October 31, 2008
    Publication date: September 24, 2009
    Inventors: Hsiang-Ming HUANG, An-Hong Liu, Yi-Chang Lee, Hao-Yin Tsai, Shu-Ching Ho