Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: Described is a system for computing conditional probabilities of random variables for Bayesian inference. The system implements a spiking neural network of neurons to compute the conditional probability of two random variables X and Y. The spiking neural network includes an increment path for a synaptic weight that is proportional to a product of the synaptic weight and a probability of X, a decrement path for the synaptic weight that is proportional to a probability of X, Y, and delay and spike timing dependent plasticity (STDP) parameters such that the synaptic weight increases and decreases with the same magnitude for a single firing event.

Abstract: Described is a system for computing conditional probabilities of random variables for Bayesian inference. The system implements a spiking neural network of neurons to compute the conditional probability of two random variables X and Y. The spiking neural network includes an increment path for a synaptic weight that is proportional to a product of the synaptic weight and a probability of X, a decrement path for the synaptic weight that is proportional to a probability of X, Y, and delay and spike timing dependent plasticity (STDP) parameters such that the synaptic weight increases and decreases with the same magnitude for a single firing event.

Abstract: A circuit that makes use of chaos or self-organized criticality to generate a matrix of bits for computation and information processing. The example embodiment utilizes CMOS circuitry and can solve optimization problems. A plurality of unit cells includes multiple transistors in a lattice formation that set voltages as state variables to other transistor cells. Adjustable bifurcation parameters are utilized to bring the chaotic circuit in and out of the chaotic regime. A processing unit with software are utilized for implanting a problem of interest into the chaotic circuit, while data latches or analog to digital converters provide for reading out the voltages from the chaotic circuit.

Abstract: A circuit that makes use of chaos or self-organized criticality to generate a matrix of bits for computation and information processing. The example embodiment utilizes CMOS circuitry and can solve optimization problems. A plurality of unit cells includes multiple transistors in a lattice formation that set voltages as state variables to other transistor cells. Adjustable bifurcation parameters are utilized to bring the chaotic circuit in and out of the chaotic regime. A processing unit with software are utilized for implanting a problem of interest into the chaotic circuit, while data latches or analog to digital converters provide for reading out the voltages from the chaotic circuit.