Patents by Inventor Hao-Yuan Lin
Hao-Yuan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953740Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.Type: GrantFiled: May 14, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Publication number: 20240113071Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
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Patent number: 11947173Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: GrantFiled: May 5, 2023Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 10539972Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.Type: GrantFiled: December 26, 2017Date of Patent: January 21, 2020Assignee: MEDIATEK INC.Inventors: Chin-Hsun Chen, Hao-Yuan Lin, Chia-Hua Chou
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Patent number: 10444779Abstract: A low dropout voltage regulator for generating an output regulated voltage is provided. The low dropout voltage regulator includes a first transistor and a current recycling circuit. The first transistor has a first terminal for receiving an input supply voltage, a second terminal for generating the output regulated voltage, and a control terminal for receiving a control voltage. The current recycling circuit is configured to drain a feeding current to the second terminal of the first transistor in response to a first signal having feedback information of the output regulated voltage.Type: GrantFiled: October 12, 2017Date of Patent: October 15, 2019Assignee: MEDIATEK INC.Inventors: Hao-Yuan Lin, Chia-Hua Chou, Yen-Hsun Hsu
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Publication number: 20180120874Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.Type: ApplicationFiled: December 26, 2017Publication date: May 3, 2018Inventors: Chin-Hsun Chen, Hao-Yuan Lin, Chia-Hua Chou
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Publication number: 20180120880Abstract: A low dropout voltage regulator for generating an output regulated voltage is provided. The low dropout voltage regulator includes a first transistor and a current recycling circuit. The first transistor has a first terminal for receiving an input supply voltage, a second terminal for generating the output regulated voltage, and a control terminal for receiving a control voltage. The current recycling circuit is configured to drain a feeding current to the second terminal of the first transistor in response to a first signal having feedback information of the output regulated voltage.Type: ApplicationFiled: October 12, 2017Publication date: May 3, 2018Inventors: Hao-Yuan Lin, Chia-Hua Chou, Yen-Hsun Hsu
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Patent number: 9886044Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.Type: GrantFiled: February 15, 2016Date of Patent: February 6, 2018Assignee: MEDIATEK INC.Inventors: Chin-Hsun Chen, Hao-Yuan Lin, Chia-Hua Chou
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Patent number: 9570990Abstract: A knee voltage detector for a flyback converter is provided. The knee voltage detector comprises a delay unit, for delaying an auxiliary related voltage for a specific period, to generate a delay signal; a subtracting unit, for generating a subtraction signal according to the auxiliary related voltage and the delay signal; a comparing unit, for generating a sampling signal when the subtraction signal indicates that a voltage difference between the auxiliary related voltage and the delay signal is greater than a threshold; and a sample and hold unit, for sampling the delay signal to generate a knee voltage according to the sampling signal when the voltage difference between the auxiliary related voltage and the delay signal is greater than the threshold.Type: GrantFiled: May 19, 2015Date of Patent: February 14, 2017Assignee: NOVATEK Microelectronics Corp.Inventors: Ke-Horng Chen, Chao-Chang Chiu, Hao-Yuan Lin, Che-Hao Meng, Chih-Wei Chang, Ying-Hsiang Wang
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Publication number: 20170038783Abstract: A dynamic current sink includes the following elements. A voltage comparator compares a reference voltage with a second control signal from an LDO (Low Dropout Linear Regulator) to generate a first control signal. A first transistor selectively pulls down a voltage at a first node according to the first control signal. The inverter is coupled between the first node and a second node. An NAND gate has a first input terminal coupled to a second transistor and a third node, a second input terminal coupled to the second node, and an output terminal coupled to a fourth node. A capacitor is coupled between the fourth node and a fifth node. A resistor is coupled between the fifth node and a ground voltage. A third transistor has a control terminal coupled to the fifth node, and selectively draws a discharge current from an output node of the LDO.Type: ApplicationFiled: February 15, 2016Publication date: February 9, 2017Inventors: Chin-Hsun CHEN, Hao-Yuan LIN, Chia-Hua CHOU
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Publication number: 20160211755Abstract: A knee voltage detector for a flyback converter is provided. The knee voltage detector comprises a delay unit, for delaying an auxiliary related voltage for a specific period, to generate a delay signal; a subtracting unit, for generating a subtraction signal according to the auxiliary related voltage and the delay signal; a comparing unit, for generating a sampling signal when the subtraction signal indicates that a voltage difference between the auxiliary related voltage and the delay signal is greater than a threshold; and a sample and hold unit, for sampling the delay signal to generate a knee voltage according to the sampling signal when the voltage difference between the auxiliary related voltage and the delay signal is greater than the threshold.Type: ApplicationFiled: May 19, 2015Publication date: July 21, 2016Inventors: Ke-Horng Chen, Chao-Chang Chiu, Hao-Yuan Lin, Che-Hao Meng, Chih-Wei Chang, Ying-Hsiang Wang