Patents by Inventor Hao-Yun Cheng
Hao-Yun Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12237402Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.Type: GrantFiled: November 28, 2022Date of Patent: February 25, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Shu-Wei Hsu, Yu-Jen Shen, Hao-Yun Cheng, Chih-Wei Wu, Ying-Tsung Chen, Ying-Ho Chen
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Publication number: 20240387699Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.Type: ApplicationFiled: July 26, 2024Publication date: November 21, 2024Inventors: Shu-Wei Hsu, Yu-Jen Shen, Hao-Yun Cheng, Chih-Wei Wu, Ying-Tsung Chen, Ying-Ho Chen
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Patent number: 12136662Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.Type: GrantFiled: November 28, 2022Date of Patent: November 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Shu-Wei Hsu, Yu-Jen Shen, Hao-Yun Cheng, Chih-Wei Wu, Ying-Tsung Chen, Ying-Ho Chen
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Publication number: 20230093717Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.Type: ApplicationFiled: November 28, 2022Publication date: March 23, 2023Inventors: Shu-Wei Hsu, Yu-Jen Shen, Hao-Yun Cheng, Chih-Wei Wu, Ying-Tsung Chen, Ying-Ho Chen
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Patent number: 11515403Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.Type: GrantFiled: November 27, 2019Date of Patent: November 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Wei Hsu, Yu-Jen Shen, Hao-Yun Cheng, Chih-Wei Wu, Ying-Tsung Chen, Ying-Ho Chen
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Publication number: 20210159325Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.Type: ApplicationFiled: November 27, 2019Publication date: May 27, 2021Inventors: Shu-Wei Hsu, Yu-Jen Shen, Hao-Yun Cheng, Chih-Wei Wu, Ying-Tsung Chen, Ying-Ho Chen
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Publication number: 20210023678Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.Type: ApplicationFiled: October 12, 2020Publication date: January 28, 2021Inventors: Chih-Wen Liu, Hao-Yun Cheng, Che-Hao Tu, Kei-Wei Chen
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Patent number: 10800004Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.Type: GrantFiled: January 18, 2019Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Wen Liu, Hao-Yun Cheng, Che-Hao Tu, Kei-Wei Chen
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Publication number: 20200101582Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.Type: ApplicationFiled: January 18, 2019Publication date: April 2, 2020Inventors: Chih-Wen Liu, Hao-Yun Cheng, Che-Hao Tu, Kei-Wei Chen