Abstract: A system and method are provided for automatic correction of numeric input, such as telephone numbers. The communications device configured to perform automatic correction can receive a numeric input string indicating a numerical address with which to initiate a communication, and compare the numeric input string to a database of known valid numerical addresses. Then, upon determining that the numeric input string has no match within the database of known valid numerical addresses, the communications device can identify a known valid numerical address that is within a threshold similarity to the numeric input string, and correct the numeric input string. The communications device can initiate communication using the corrected numeric input string. Also set forth herein are a system and method for automatic completion of partially entered numerical addresses.

Abstract: A system and method are provided for automatic correction of numeric input, such as telephone numbers. The communications device configured to perform automatic correction can receive a numeric input string indicating a numerical address with which to initiate a communication, and compare the numeric input string to a database of known valid numerical addresses. Then, upon determining that the numeric input string has no match within the database of known valid numerical addresses, the communications device can identify a known valid numerical address that is within a threshold similarity to the numeric input string, and correct the numeric input string. The communications device can initiate communication using the corrected numeric input string. Also set forth herein are a system and method for automatic completion of partially entered numerical addresses.

Abstract: The invention provides a method and system for performing Static Timing Analysis on SoC (System on a Chip) designs. The invention solves a longstanding problem with timing analysis of designs, namely, the ability to multi-thread the design under analysis. The invention provides for slicing a design into levels, further decomposing each level into gates, and the multi-threaded processing of gates so that the solution of large design analysis is generated significantly faster than current approaches. Further, the invention provides that only one level exists in the RAM at any time. Once the arrival time on the level is computed, the data is saved to disk immediately. Because the memory footprint is sub-linear to the size of the design, entire system-on-a chip designs may be run on inexpensive, off-the-shelf hardware.

Abstract: The invention provides a method and system for performing Static Timing Analysis on SoC (System on a Chip) designs. The invention solves a longstanding problem with timing analysis of designs, namely, the ability to multi-thread the design under analysis. The invention provides for slicing a design into levels, further decomposing each level into gates, and the multi-threaded processing of gates so that the solution of large design analysis is generated significantly faster than current approaches. Further, the invention provides that only one level exists in the RAM at any time. Once the arrival time on the level is computed, the data is saved to disk immediately. Because the memory footprint is sub-linear to the size of the design, entire system-on-a chip designs may be run on inexpensive, off-the-shelf hardware.

Abstract: The invention provides a method and system for performing Static Timing Analysis on SoC (System on a Chip) designs. The invention solves a longstanding problem with timing analysis of designs, namely, the ability to multi-thread the design under analysis. The invention provides for slicing a design into levels, further decomposing each level into gates, and the multi-threaded processing of gates so that the solution of large design analysis is generated significantly faster than current approaches. Further, the invention provides that only one level exists in the RAM at any time. Once the arrival time on the level is computed, the data is saved to disk immediately. Because the memory footprint is sub-linear to the size of the design, entire system-on-a chip designs may be nm on inexpensive, off-the-shelf hardware.

Abstract: The invention provides a method and system for performing Static Timing Analysis on SoC (System on a Chip) designs. The invention solves a longstanding problem with timing analysis of designs, namely, the ability to multi-thread the design under analysis. The invention provides for slicing a design into levels, further decomposing each level into gates, and the multi-threaded processing of gates so that the solution of large design analysis is generated significantly faster than current approaches. Further, the invention provides that only one level exists in the RAM at any time. Once the arrival time on the level is computed, the data is saved to disk immediately. Because the memory footprint is sub-linear to the size of the design, entire system-on-a chip designs may be nm on inexpensive, off-the-shelf hardware.