Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer including first dies in a first insulating material; a second layer on the first layer, the second layer including second dies and third dies in a second insulating material, the second dies having a first thickness, the third dies having a second thickness different than the first thickness, and the second dies and the third dies having a surface, wherein the surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways through the RDL, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways through the RDL and by interconnects.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer having first dies in a first insulating material; a second layer on the first layer, the second layer including second dies having a first thickness and third dies having a second thickness different than the first thickness, the second dies and the third dies in a second insulating material, wherein the second dies and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3,000 square millimeters (mm2) and 9,000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including conductive pathways, wherein the first dies are electrically coupled to the second dies and the third dies by the conductive pathways and by interconnects.

Abstract: Embodiments disclosed herein include package substrates with bridge dies. In an embodiment, an apparatus comprises a first layer that is a glass layer. A via is provided through the first layer, where the via is electrically conductive. In an embodiment, a second layer is over the first layer, and the second layer comprises an organic dielectric material. In an embodiment, a cavity is provided in the second layer, where the via is within a footprint of the cavity. In an embodiment, a die is in the cavity. In an embodiment, the die is electrically coupled to the via.

Abstract: An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to enable electrical traces on glass cores in integrated circuit packages that includes an integrated circuit (IC) package substrate comprising a glass core, a photo-imageable dielectric (PID) material on the glass core, and metal interconnects in openings in the PID material.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a package substrate, and a first pad over the package substrate. In an embodiment, a layer is over the package substrate, where the layer is an insulating material. In an embodiment, the electronic package further comprises a via through the layer and in contact with the first pad. In an embodiment a first end of the via has a first width and a second end of the via that is in contact with the first pad has a second width that is larger than the first width. In an embodiment, the electronic package further comprises a second pad over the via.

Abstract: An electronic device includes a substrate including a core layer; a cavity formed in the core layer, wherein the cavity includes sidewalls plated with a conductive material; a prefabricated passive electronic component disposed in the cavity; and a cavity sidewall connection providing electrical continuity from the plated cavity sidewalls to a first surface of the substrate and to a second surface of the substrate.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed that adhere a dielectric to a nonconductive layer in circuit devices. An example apparatus includes an electrically conductive layer, a dielectric layer, and an electrically nonconductive layer separating the dielectric layer from the conductive layer, the nonconductive layer having a first surface facing the conductive layer and a second surface facing the dielectric layer, the first surface having a first roughness, the second surface having a second roughness greater than the first roughness.

Abstract: Recesses formed at the tops and bottoms of through glass via (TGV) metal regions during TGV formation can create glass-metal-air triple points. These triple points can be the source of cracks or other damage to a glass layer during thermal treatment in downstream processing due to the coefficient of thermal expansion mismatch between the TGV metal and the glass. To relieve stress at the triple points, the recesses can be filled with a conductive paste or a metal layer formed via electroless plating. Alternatively, during TGV formation, regions of low-modulus dielectric material can be formed where the triple points would otherwise be formed. The low-modulus dielectric material can provide local stress relief and mitigate the formation of glass layer damage in downstream processing.

Abstract: Recesses formed at the tops and bottoms of through glass via (TGV) metal regions during TGV formation can create glass-metal-air triple points. These triple points can be the source of cracks or other damage to a glass layer during thermal treatment in downstream processing due to the coefficient of thermal expansion mismatch between the TGV metal and the glass. To relieve stress at the triple points, the recesses can be filled with a conductive paste or a metal layer formed via electroless plating. Alternatively, during TGV formation, regions of low-modulus dielectric material can be formed where the triple points would otherwise be formed. The low-modulus dielectric material can provide local stress relief and mitigate the formation of glass layer damage in downstream processing.

Abstract: An apparatus comprising a package substrate, the package substrate comprising a glass structure; at least one buildup layer above the glass structure; and at least one buildup layer below the glass structure; wherein the glass structure comprises a first portion having a first thickness and a second portion that extends outward from the first portion, wherein the second portion has a second thickness that is smaller than the first thickness.

Abstract: 3D printing material in direct contact with edge of a glass core in IC packages to additively form a frame. Multiple such cores may be reconstituted into a panel that may then be built-up with routing metallization and assembled with IC die. Layers of printed material may be built up to form a frame with approximately the same thickness as the glass core and of any desired lateral width. The printed material may be an organic polymer or inorganic composition including metallics and ceramics. Beads of different material composition may be printed in succession to vary mechanical, electrical and/or thermal properties. A portion of the protective frame may be retained on an edge of the glass core when panels are singulated into package substrate units. Frame material may also be printed upon edges of glass-cored package units after their singulation.

Abstract: Embodiments disclosed herein may include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material. In an embodiment, a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, the apparatus may further comprise a layer surrounding a perimeter of the first substrate, the second substrate, and the third substrate, where the layer comprises a dielectric material, with a fourth edge of the layer that is substantially linear. In an embodiment, a frame surrounds and contacts the fourth edge of the layer.

Abstract: Embodiments disclosed herein include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material, and where a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, a layer contacts the first substrate, the second substrate, and the third substrate, where a portion of an outer sidewall of the layer is substantially parallel to the first edge of the first substrate.

Abstract: Integrated circuit (IC) devices having glass layers in package substrates. An IC device substrate may include a solid glass layer and a polymer layer that forms a frame on sidewalls and an upper surface of the glass layer, and the glass layer may include a tab or nubbin that extends through the frame of the polymer layer. The substrate may include electrical vias through the substrate and electrical traces on one or both sides of the substrate. Portions of a glass panel (for example, along saw streets) may be removed and replaced with polymer frame materials. The glass panel may be sawn into glass substrates by sawing through the polymer and through glass bridge portions, which may be of minimal thickness.

Abstract: Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a first surface, a second surface opposite the first surface, and a side surface extending between the first surface and the second surface, wherein the side surface protrudes at a middle of the glass layer; a dielectric layer at the first surface of the glass layer; and a recess in the dielectric layer at the first surface of the glass layer. In other embodiments, a microelectronic assembly may include a dielectric layer at a surface of a glass layer and a material along a side surface of the dielectric layer, the material including a dry film photoresist, a water-soluble material, a thermal decomposable material, or a non-filled polymeric material. In other embodiments, the dielectric layer may include a conductive bulk material along a side surface.

Abstract: According to the various aspects, a method is provided for dicing a semiconductor panel having a glass core with topside build-up (BU) layers, backside BU layers, and interconnects. In an aspect, a hard mask is deposited on the semiconductor panel and patterned to form openings for a plurality of cut-streets. In an aspect, the dicing of the semiconductor panel includes using plasma dicing steps to form cut-streets through the topside BU layers and the backside BU layers, and using a mechanical sawing step or plasma dicing step to cut through the glass core. In another aspect, the dicing of the semiconductor panel further includes using an acid rinse to remove metal salts when cutting through the glass core during the plasma dicing step. In another aspect, a singulated die may have a first BU sidewall and a second BU sidewall having a morphology that includes semi-sphere fillers.

Abstract: Microelectronic assemblies with glass cores with tapered insulator edges, as well as related devices and fabrication techniques, are disclosed. In one aspect, a microelectronic assembly according to an embodiment of the present disclosure may include a glass core (e.g., a layer of glass or a glass structure) having a first face, and an insulator material having a bottom face, a top face opposite the bottom face, and an outer edge extending between the bottom face and the top face. The top bottom face of the insulator material is on the glass core, and the outer edge of the insulator material tapers from a first perimeter at the bottom face to a second perimeter at the top face. The taper of the outer edge results in the first perimeter being larger than the second perimeter.

Abstract: A die assembly is disclosed. The die assembly includes a die, one or more die pads on a first surface of the die and a die attach film on the die where the die attach film includes one or more openings that expose the one or more die pads and that extend to one or more edges of the die.

Abstract: An apparatus comprising a package substrate, the package substrate comprising a glass layer, a first layer comprising a photo-imageable dielectric (PID) material above the glass layer, a second layer below the glass layer, the second layer comprising the PID material, at least one buildup layer above the first layer, and at least one buildup layer below the second layer.