Patents by Inventor Haofeng SHEN

Haofeng SHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10943994
    Abstract: A manufacturing method for a shielded gate trench device comprises the following steps: Step 1, forming a gate trench in a first epitaxial layer; Step 2, forming a first dielectric layer and fully filling the gate trench with a first polysilicon layer; Step 3, forming a top trench: Step 31, carrying out primary polysilicon dry-etching; Step 32, carrying out primary dielectric layer wet-etching to decrease the thickness of the first dielectric layer in the top trench; Step 33, carrying out secondary polysilicon dry-etching; Step 34, carrying out secondary dielectric layer wet-etching to remove the rest of the first dielectric layer on a side face of the top trench and to form the top trench; and Step 4, forming a trench gate in the top trench. By adoption of the manufacturing method, the gate-source capacitance and the gate-drain capacitance can be decreased, and thus, the input capacitance is decreased.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: March 9, 2021
    Assignee: Shanhai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Yulong Yang, Zhengrong Chen, Haofeng Shen
  • Publication number: 20200295159
    Abstract: A manufacturing method for a shielded gate trench device comprises the following steps: Step 1, forming a gate trench in a first epitaxial layer; Step 2, forming a first dielectric layer and fully filling the gate trench with a first polysilicon layer; Step 3, forming a top trench: Step 31, carrying out primary polysilicon dry-etching; Step 32, carrying out primary dielectric layer wet-etching to decrease the thickness of the first dielectric layer in the top trench; Step 33, carrying out secondary polysilicon dry-etching; Step 34, carrying out secondary dielectric layer wet-etching to remove the rest of the first dielectric layer on a side face of the top trench and to form the top trench; and Step 4, forming a trench gate in the top trench. By adoption of the manufacturing method, the gate-source capacitance and the gate-drain capacitance can be decreased, and thus, the input capacitance is decreased.
    Type: Application
    Filed: December 6, 2019
    Publication date: September 17, 2020
    Applicant: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
    Inventors: Yulong YANG, Zhengrong CHEN, Haofeng SHEN