Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a structure strengthen plug in an upper portion of the alternating dielectric stack, wherein the structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a gate line silt in the alternating dielectric stack to expose a sidewall of one enlarged connecting portion of the structure strengthen plug; and forming a gate line slit structure in the gate line slit including an enlarged end portion connected to the one enlarged connecting portion of the structure strengthen plug.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure including a memory block including a plurality of memory cells. The 3D memory device also includes a first top select structure and a bottom select structure in the memory block and aligned with each other vertically; and a second top select structure in the memory block is separated from the first top select structure by at least one of the plurality of memory cells. The first top select structure, the bottom select structure, and the second top select structure each includes an insulating material.

Abstract: Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer.

Abstract: In a three-dimensional memory device, an interconnect structure is formed over a substrate and a first deck is formed over the interconnect structure. The first deck includes alternating first insulating layers and first word line layers, and a first channel structure extending through the first stack. The first channel structure has a first channel dielectric region and a first channel layer. The first channel dielectric region is formed along sidewalls of the first channel structure, positioned over a top surface of the interconnect structure, and in contact with the first insulating layers and the first word line layers. The first channel layer is formed along the first channel dielectric region, and includes a rounded projection that extends away from the top surface of the interconnect structure, extends outwards into the first stack at an interface of the interconnect structure, the first channel structure and the first stack.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a method for forming a 3D memory device includes forming a bottom select structure extending along a vertical direction through a bottom conductor layer over a substrate and along a horizontal direction to divide the bottom conductor layer into a pair of bottom select conductor layers, forming a plurality of conductor layers and a plurality of insulating layers interleaved on the pair of bottom select conductor layers and the bottom select structure, and forming a plurality of channel structures extending along the vertical direction through the pair of bottom select conductor layers, the plurality of conductor layers, and the plurality of insulating layers and into the substrate.

Abstract: A three-dimensional (3D) memory device includes a memory stack including interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack, a memory block including a plurality of channel structures extending vertically through the memory stack, a plurality of source structures extending vertically and laterally in the memory stack and being in contact with the memory block, and a plurality of conductor portions and a plurality of insulating portions being interleaved and locating between two adjacent source structures along a direction which the source structure extends. The interleaved plurality of conductor portions and plurality of insulating portions are each in contact with corresponding conductor layers and corresponding insulating layers of the same level from adjacent memory blocks.

Abstract: In a three-dimensional memory device, an interconnect structure is formed over a substrate and a first deck is formed over the interconnect structure. The first deck includes alternating first insulating layers and first word line layers, and a first channel structure extending through the first stack. The first channel structure has a first channel dielectric region and a first channel layer. The first channel dielectric region is formed along sidewalls of the first channel structure, positioned over a top surface of the interconnect structure, and in contact with the first insulating layers and the first word line layers. The first channel layer is formed along the first channel dielectric region, and includes a rounded projection that extends away from the top surface of the interconnect structure, extends outwards into the first stack at an interface of the interconnect structure, the first channel structure and the first stack.

Abstract: A method for forming a 3D memory device is provided. The method includes forming a dielectric stack including interleaved initial insulating layers and initial sacrificial layers over a substrate, and forming at least one slit structure extending vertically and laterally in the dielectric stack and dividing the dielectric stack into block regions. The at least one slit structure each includes slit openings exposing the substrate and an initial support structure between adjacent slit openings. Each block region may include interleaved insulating layers and sacrificial layers, and the initial support structure may include interleaved insulating portions and sacrificial portions. Each insulating portion and sacrificial portion may be in contact with respective insulating layers and sacrificial layers of a same level from adjacent block regions.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.

Abstract: A semiconductor device includes a string of transistors stacked along a vertical direction above a substrate of the semiconductor device. The string can include a first substring, a channel connector disposed above the first substring, and a second substring. The first substring includes a first channel structure having a first channel layer and a first gate dielectric structure that extend along the vertical direction. The second substring is stacked above the channel connector, and has a second channel structure that includes a second channel layer and a second gate dielectric structure that extend along the vertical direction. The channel connector, electrically coupling the first and the second channel layer, is disposed below the second gate dielectric structure to enable formation of a conductive path in a bottom region of the second channel layer. The bottom region is associated with a lowermost transistor in the second substring.

Abstract: A method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure including a memory block including a plurality of memory cells. The 3D memory device also includes a first top select structure and a bottom select structure in the memory block and aligned with each other vertically; and a second top select structure in the memory block is separated from the first top select structure by at least one of the plurality of memory cells. The first top select structure, the bottom select structure, and the second top select structure each includes an insulating material.

Abstract: Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a structure strengthen plug in an upper portion of the alternating dielectric stack, wherein the structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a gate line silt in the alternating dielectric stack to expose a sidewall of one enlarged connecting portion of the structure strengthen plug; and forming a gate line slit structure in the gate line slit including an enlarged end portion connected to the one enlarged connecting portion of the structure strengthen plug.

Abstract: Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. The method includes: forming an alternating dielectric stack on a substrate; forming a top selective gate cut and two structure strengthen plugs in an upper portion of the alternating dielectric stack, wherein each structure strengthen plug has a narrow support body and two enlarged connecting portions; forming a plurality of channel structures in the alternating dielectric stack; forming a plurality of gate line silts in the alternating dielectric stack, wherein each gate line slit exposes a sidewall of one enlarged connecting portion of a corresponding structure strengthen plug; transforming the alternating dielectric stack into an alternating conductive/dielectric stack; and forming a gate line slit structure in each gate line slit including an enlarged end portion connected to one enlarged connecting portion of a corresponding structure strengthen plug.

Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the 3D memory device includes a stack structure. The stack structure includes a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate. The plurality of conductor layers include a pair of top select conductor layers divided by a first top select structure and a pair of bottom select conductor layers divided by a bottom select structure. The first top select structure and the bottom select structure extend along a horizontal direction and are aligned along a vertical direction. A plurality of channel structures extend along a vertical direction and into the substrate and are distributed on both sides of the top select structure and the bottom select structure.

Abstract: Aspects of the disclosure provide methods for manufacturing semiconductor devices. One of the methods forms a string of transistors in a semiconductor device over a substrate of the semiconductor device. The method includes forming a first substring of transistors having a first channel structure that includes a first channel layer and a first gate dielectric structure that extend along a vertical direction over the substrate. The method includes forming a channel connector over the first substring and forming the second substring above the channel connector. The second substring has a second channel structure. The second channel structure includes the second channel layer and a second gate dielectric structure that extend along the vertical direction. The second gate dielectric structure is formed above the channel connector. The channel connector electrically couples the first channel layer and the second channel layer.