Patents by Inventor Haojun Zhang

Haojun Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12155125
    Abstract: An electronic device and a method for fabricating an antenna radiator are provided. The electronic device includes a circuit board, a support, a back cover, and a first antenna radiator located on the support, and a second antenna radiator located on one side of the back cover. The first antenna radiator and the second antenna radiator are electromagnetically coupled and connected. The first antenna radiator is able to radiate a wireless signal of a first wavelength, and the second antenna radiator is able to radiate a wireless signal of a second wavelength which is half of the first wavelength.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: November 26, 2024
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Haojun Zhang
  • Publication number: 20230125453
    Abstract: A method for improving a heat dissipation capability of an oil-cooled motor, insulation paint, and a method for manufacturing the insulation paint. The method includes: performing insulation processing on a motor component by using insulation paint, where the motor component includes a stator winding and/or a rotor winding; and installing the motor component undergoing the insulation processing into an oil-cooled motor, where a basic component of the insulation paint is unsaturated polyesterimine modified by using an inorganic layered silicate. The insulation paint has high heat conductivity, high heat resistance, and low viscosity, and therefore can improve a heat dissipation capability of the oil-cooled motor in a use process, and reduce a temperature rise of the oil-cooled motor in the use process, thereby improving power of the oil-cooled motor and prolonging a service life of the oil-cooled motor.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 27, 2023
    Applicant: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Liuqing YANG, Xiaohong CHI, Zezhao BAI, Haojun ZHANG, Zijing WANG
  • Patent number: 11594462
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: February 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet S. Gandhi
  • Publication number: 20220181793
    Abstract: An electronic device and a method for fabricating an antenna radiator are provided. The electronic device includes a circuit board, a support, a back cover, and a first antenna radiator located on the support, and a second antenna radiator located on one side of the back cover. The first antenna radiator and the second antenna radiator are electromagnetically coupled and connected. The first antenna radiator is able to radiate a wireless signal of a first wavelength, and the second antenna radiator is able to radiate a wireless signal of a second wavelength which is half of the first wavelength.
    Type: Application
    Filed: February 25, 2022
    Publication date: June 9, 2022
    Inventor: Haojun ZHANG
  • Patent number: 10833012
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 10, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chien-Hsin Lee, Haojun Zhang, Mahadeva Iyer Natarajan
  • Publication number: 20200350224
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Application
    Filed: July 23, 2020
    Publication date: November 5, 2020
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet S. Gandhi
  • Patent number: 10741468
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet S. Gandhi
  • Publication number: 20200027826
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: CHIEN-HSIN LEE, HAOJUN ZHANG, MAHADEVA IYER NATARAJAN
  • Patent number: 10510663
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chien-Hsin Lee, Haojun Zhang, Mahadeva Iyer Natarajan
  • Patent number: 10403622
    Abstract: Structures for a frequency divider, methods of fabricating a frequency divider, and method of using a frequency divider. A first interconnect line is configured to selectively conduct a first signal of a first frequency. A second interconnect line is coupled with the first interconnect line. The second interconnect line is configured to selectively conduct a second signal of a second frequency. The first frequency is less the second frequency.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: September 3, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mahadeva Iyer Natarajan, Haojun Zhang, Chien-Hsin Lee
  • Publication number: 20190244954
    Abstract: Structures for a frequency divider, methods of fabricating a frequency divider, and method of using a frequency divider. A first interconnect line is configured to selectively conduct a first signal of a first frequency. A second interconnect line is coupled with the first interconnect line. The second interconnect line is configured to selectively conduct a second signal of a second frequency. The first frequency is less the second frequency.
    Type: Application
    Filed: February 6, 2018
    Publication date: August 8, 2019
    Inventors: Mahadeva Iyer Natarajan, Haojun Zhang, Chien-Hsin Lee
  • Publication number: 20190122950
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet S. Gandhi
  • Patent number: 10170389
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: January 1, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet S. Gandhi
  • Patent number: 10153224
    Abstract: Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate; providing a plate parallel to and spaced from the backside of the substrate; and forming a TIM layer, surrounding the vertical spacers, between the backside of the substrate and the plate.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: December 11, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Rahul Agarwal, Luke England, Haojun Zhang
  • Publication number: 20180286801
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Inventors: CHIEN-HSIN LEE, HAOJUN ZHANG, MAHADEVA IYER NATARAJAN
  • Publication number: 20180076110
    Abstract: Methods for reducing the junction temperature between an IC chip and its lid by including metal spacers in the TIM layer and the resulting devices are disclosed. Embodiments include providing a substrate, including integrated circuit devices, having front and back sides; forming vertical spacers on the backside of the substrate; providing a plate parallel to and spaced from the backside of the substrate; and forming a TIM layer, surrounding the vertical spacers, between the backside of the substrate and the plate.
    Type: Application
    Filed: September 14, 2016
    Publication date: March 15, 2018
    Inventors: Rahul AGARWAL, Luke ENGLAND, Haojun ZHANG
  • Publication number: 20160244905
    Abstract: A washing machine and a washing control method of the washing machine thereof. The washing machine includes an outer drum, an inner drum, an impeller, and a driving apparatus. The driving apparatus is a dual-rotor direct drive motor including two rotors and one stator. One rotor is axially connected to the inner drum, another rotor is axially connected to the impeller. During washing, the two rotors respectively drive the impeller and the inner drum to rotate independently, such that the inner drum and the impeller rotate opposite to each other, and after each rotation cycle, the inner drum and the impeller reversely rotate. The washing control method includes driving, the driving apparatus, the inner drum and the impeller to reverse asynchronously, so as to enable the impeller and the inner drum to rotate in a same direction within a time difference between reversals of the impeller and the inner drum.
    Type: Application
    Filed: December 18, 2013
    Publication date: August 25, 2016
    Inventors: Peishi LV, Qiuying GAO, Jie XU, Dafeng FANG, Haojun ZHANG
  • Publication number: 20150348956
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Application
    Filed: August 12, 2015
    Publication date: December 3, 2015
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijan Luo, Luke G. England, Brent Keeth, Jaspreet S. Gandhi
  • Patent number: 9153520
    Abstract: Stacked semiconductor die assemblies with multiple thermal paths and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a plurality of first semiconductor dies arranged in a stack and a second semiconductor die carrying the first semiconductor dies. The second semiconductor die can include a peripheral portion that extends laterally outward beyond at least one side of the first semiconductor dies. The semiconductor die assembly can further include a thermal transfer feature at the peripheral portion of the second semiconductor die. The first semiconductor dies can define a first thermal path, and the thermal transfer feature can define a second thermal path separate from the first semiconductor dies.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 6, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Steven K. Groothuis, Jian Li, Haojun Zhang, Paul A. Silvestri, Xiao Li, Shijian Luo, Luke G. England, Brent Keeth, Jaspreet Gandhi
  • Patent number: 8688113
    Abstract: The present invention discloses a method and a system for implementing location service, in which the method comprises: sending a location request message from a source user to a MMSG by a MMSC; sending the location request message to a multimedia message generating platform by the MMSG; initiating a location request to an LSP by the multimedia message generating platform according to the location request message; performing location according to the initiated location request and returning a location result to the multimedia message generating platform by the LSP; generating multimedia message information according to the location result and sending the multimedia message information to the MMSG by the multimedia message generating platform; and sending the received multimedia message information to the source user through the MMSC by the MMSG.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: April 1, 2014
    Assignee: ZTE Corporation
    Inventors: Guocai Wang, Haojun Zhang