Patents by Inventor Haoning ZHENG
Haoning ZHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11984496Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DEG.Type: GrantFiled: April 22, 2020Date of Patent: May 14, 2024Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventors: Anbang Zhang, King Yuen Wong, Hao Li, Haoning Zheng, Jian Wang
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Publication number: 20240154012Abstract: A semiconductor device includes a first and a second nitride-based semiconductor layers and a gate structure. The gate structure includes an outer spacer, an inner spacer and a gate electrode. The outer spacer has at least two opposite inner sidewalls to define a gate trench. The inner spacer is within the gate trench. The gate electrode disposed in the gate trench and covered by the inner spacer, wherein the inner spacer and the gate electrode extend downward to collaboratively form a bottom portion of the gate structure with a first width greater than a second width of a bottom surface of the gate electrode.Type: ApplicationFiled: March 29, 2022Publication date: May 9, 2024Inventors: Yang LIU, Liang CHEN, Xiao ZHANG, Haoning ZHENG, King Yuen WONG
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Patent number: 11961902Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DEG.Type: GrantFiled: April 22, 2020Date of Patent: April 16, 2024Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventors: Anbang Zhang, King Yuen Wong, Hao Li, Haoning Zheng, Jian Wang
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Patent number: 11942525Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor heterostructure layer and a conductive structure. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. 2DHGs may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. The conductive structure includes a plurality of conductive fingers extending from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction, so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DHG.Type: GrantFiled: April 22, 2020Date of Patent: March 26, 2024Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventors: Anbang Zhang, King Yuen Wong, Hao Li, Haoning Zheng, Jian Wang
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Patent number: 11637177Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a first III-nitride layer, a second III-nitride layer, a first contact layer, a second contact layer, a structure, and a gate layer. The second III-nitride layer is in direct contact with the first III-nitride layer. The first contact layer and the second contact layer are disposed over the second III-nitride layer. The structure is adjacent to an interface of the first III-nitride layer and the second III-nitride layer, and a material of the structure is different from a material of the first III-nitride layer or a material of the second III-nitride layer. The gate layer is disposed between the first contact layer and the second contact layer.Type: GrantFiled: April 13, 2020Date of Patent: April 25, 2023Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventors: Hao Li, Anbang Zhang, Jian Wang, Haoning Zheng
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Patent number: 11588047Abstract: The present disclosure discloses a semiconductor component and a method for forming the semiconductor component. The semiconductor component includes a substrate, a III-V layer, a doped III-V layer, a gate contact, a first field plate, and a second field plate. The gate contact has first and second sides away from the doped III-V layer. The first field plate has first and second sides, and the first side is closer to the second side of the gate contact than the second side. The second field plate has first and second sides, and the first side is closer to the second side of the gate contact than the second side. The first field plate is closer to the doped III-V layer than the second field plate and the first side and the second side of the gate contact.Type: GrantFiled: August 10, 2020Date of Patent: February 21, 2023Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventors: Hao Li, Haoning Zheng, Anbang Zhang
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Publication number: 20220399444Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a semiconductor stack and a first ohmic contact. The semiconductor stack is formed on a substrate. The semiconductor stack has a first nitride semiconductor layer and a second nitride semiconductor layer formed on the first nitride semiconductor layer. The second nitride semiconductor layer has a wider bandgap than that of the first nitride semiconductor layer. The first ohmic contact is disposed over the semiconductor stack. The first to ohmic contact has a first opening exposing the first nitride semiconductor layer.Type: ApplicationFiled: January 12, 2021Publication date: December 15, 2022Inventors: Hao LI, Anbang ZHANG, Haoning ZHENG
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Publication number: 20220376070Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-nitride layer, a gate, a connection structure, and a gate bus. The gate is disposed over the III-nitride layer. The connection structure is disposed over the gate. The gate bus extends substantially in parallel to the gate and disposed over the connection structure from a top view perspective. The gate bus is electrically connected to the gate through the connection structure.Type: ApplicationFiled: June 30, 2020Publication date: November 24, 2022Inventors: Hao LI, Anbang ZHANG, Jian WANG, Haoning ZHENG
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Publication number: 20220375874Abstract: A III-nitride-based semiconductor device is provided. The III-nitride semiconductor device includes a silicon substrate having a surface with a periodic array of recesses formed therein. A discontinuous insulating layer is formed within each recess of the periodic array of recesses such that a portion of the silicon substrate surface between adjacent recesses is free from coverage of the discontinuous insulating layer. A first epitaxial III-nitride semiconductor layer is formed over the silicon substrate with the periodic array of recesses and discontinuous insulating layer formed thereon. A second III-nitride semiconductor layer is disposed over the first III-nitride semiconductor layer and has a bandgap greater than a bandgap of the first III-nitride semiconductor layer. At least one source and at least one drain are disposed over the second III-nitride semiconductor layer. A gate is also disposed over the second III-nitride semiconductor layer between the source and the drain.Type: ApplicationFiled: March 30, 2021Publication date: November 24, 2022Inventors: Liang CHEN, Hao LI, Haoning ZHENG, King Yuen WONG
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Publication number: 20220140094Abstract: The present disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor heterostructure layer and a conductive structure. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. 2DHGs may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. The conductive structure includes a plurality of conductive fingers extending from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction, so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DHG.Type: ApplicationFiled: April 22, 2020Publication date: May 5, 2022Inventors: Anbang ZHANG, King Yuen WONG, Hao LI, Haoning ZHENG, Jian WANG
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Publication number: 20220123137Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DEG.Type: ApplicationFiled: April 22, 2020Publication date: April 21, 2022Inventors: Anbang ZHANG, King Yuen WONG, Hao LI, Haoning ZHENG, Jian WANG
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Publication number: 20220123106Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a first III-nitride layer, a second III-nitride layer, a first contact layer, a second contact layer, a structure, and a gate layer. The second III-nitride layer is in direct contact with the first III-nitride layer. The first contact layer and the second contact layer are disposed over the second III-nitride layer. The structure is adjacent to an interface of the first III-nitride layer and the second III-nitride layer, and a material of the structure is different from a material of the first III-nitride layer or a material of the second III-nitride layer. The gate layer is disposed between the first contact layer and the second contact layer.Type: ApplicationFiled: April 13, 2020Publication date: April 21, 2022Inventors: HAO LI, ANBANG ZHANG, JIAN WANG, HAONING ZHENG
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Publication number: 20220115526Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different second semiconductor material layer and is not in contact with the 2DEG.Type: ApplicationFiled: April 22, 2020Publication date: April 14, 2022Inventors: Anbang ZHANG, King Yuen WONG, Hao LI, Haoning ZHENG, Jian WANG
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Publication number: 20220115527Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional hole gas (2DHG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DHG.Type: ApplicationFiled: April 22, 2020Publication date: April 14, 2022Inventors: Anbang ZHANG, King Yuen WONG, Hao LI, Haoning ZHENG, Jian WANG
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Publication number: 20210384338Abstract: The present disclosure discloses a semiconductor component and a method for forming the semiconductor component. The semiconductor component includes a substrate, a III-V layer, a doped III-V layer, a gate contact, a first field plate, and a second field plate. The gate contact has first and second sides away from the doped III-V layer. The first field plate has first and second sides, and the first side is closer to the second side of the gate contact than the second side. The second field plate has first and second sides, and the first side is closer to the second side of the gate contact than the second side. The first field plate is closer to the doped III-V layer than the second field plate and the first side and the second side of the gate contact.Type: ApplicationFiled: August 10, 2020Publication date: December 9, 2021Inventors: Hao LI, Haoning ZHENG, Anbang ZHANG