Patents by Inventor Haoqiang Zheng

Haoqiang Zheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140245304
    Abstract: Techniques for implicit coscheduling of CPUs to improve corun performance of scheduled contexts are described. One technique minimizes skew by implementing corun migrations, and another technique minimizes skew by implementing a corun bonus mechanism. Skew between schedulable contexts may be calculated based on guest progress, where guest progress represents time spent executing guest operating system and guest application code. A non-linear skew catch-up algorithm is described that adjusts the progress of a context when the progress falls far behind its sibling contexts.
    Type: Application
    Filed: May 8, 2014
    Publication date: August 28, 2014
    Applicant: VMWARE, INC.
    Inventors: Haoqiang ZHENG, Carl A. WALDSPURGER
  • Patent number: 8752058
    Abstract: Techniques for implicit co scheduling of CPUs to improve corun performance of scheduled contexts are described. One technique minimizes skew by implementing corun migrations, and another technique minimizes skew by implementing a corun bonus mechanism. Skew between schedulable contexts may be calculated based on guest progress, where guest progress represents time spent executing guest operating system and guest application code. A non-linear skew catch-up algorithm is described that adjusts the progress of a context when the progress falls far behind its sibling contexts.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: June 10, 2014
    Assignee: VMware, Inc.
    Inventors: Haoqiang Zheng, Carl A. Waldspurger
  • Publication number: 20100095300
    Abstract: Methods, computer programs, and systems for managing thread performance in a computing environment based on cache occupancy are provided. In one embodiment, a computer implemented method assigns a thread performance counter to threads being created to measure the number of cache misses for the threads. The thread performance counter is deduced in one embodiment based on performance counters associated with each core in a processor. The method further calculates a self-thread value as the change in the thread performance counter of a given thread during a predetermined period, and an other-thread value as the sum of all the changes in the thread performance counters for all threads except for the given thread. Further, the method estimates a cache occupancy for the given thread based on a previous occupancy for the given thread, and the calculated shelf-thread and other-thread values. The estimated cache occupancy is used to assign computing environment resources to the given thread.
    Type: Application
    Filed: October 14, 2008
    Publication date: April 15, 2010
    Applicant: VMWARE, INC.
    Inventors: Richard West, Puneet Zaroo, Carl A. Waldspurger, Xiao Zhang, Haoqiang Zheng